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Commit db811f3a authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'master' into L2SDP-846

parents bbfd3e44 30161261
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1 merge request!305Resolve L2SDP-846
Pipeline #42532 passed
Stage: simulation
Stage: synthesis
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libraries/technology/flash/hdllib.cfg
+ 5
− 5
View file @ db811f3a
......@@ -7,9 +7,9 @@ hdl_lib_uses_synth = technology
ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update
ip_arria10_e1sg_asmi_parallel # modelsim crashes when asmi_parallel ip is used(segmentation violation)
ip_arria10_e1sg_remote_update
ip_arria10_e2sg_asmi_parallel
ip_arria10_e2sg_remote_update
ip_arria10_e1sg_remote_update # modelsim crashes when asmi_parallel ip is used(segmentation violation)
ip_arria10_e2sg_asmi_parallel # modelsim crashes when asmi_parallel ip is used(segmentation violation)
ip_arria10_e2sg_remote_update # modelsim crashes when asmi_parallel ip is used(segmentation violation)
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
......@@ -26,8 +26,8 @@ hdl_lib_disclose_library_clause_names =
synth_files =
tech_flash_component_pkg.vhd
tech_flash_asmi_parallel.vhd #e1sg component is not instantiated in simulation
tech_flash_remote_update.vhd
tech_flash_asmi_parallel.vhd #e1sg,e2sg component is not instantiated in simulation, only for synthesis
tech_flash_remote_update.vhd #e1sg,e2sg component is not instantiated in simulation, only for synthesis
test_bench_files =
......
libraries/technology/flash/tech_flash_asmi_parallel.vhd
+ 1
− 1
View file @ db811f3a
......@@ -32,7 +32,7 @@ LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
LIBRARY ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910;
--LIBRARY ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
......
libraries/technology/flash/tech_flash_remote_update.vhd
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− 2
View file @ db811f3a
......@@ -31,8 +31,8 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_1910;
--LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
--LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_1910;
ENTITY tech_flash_remote_update IS
GENERIC (
......
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
+ 1
− 0
View file @ db811f3a
hdl_lib_name = ip_arria10_e2sg_altera_asmi_parallel_1910
# Note, this library causes modelsim to crash!
hdl_library_clause_name = altera_asmi_parallel_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
......
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+ 1
− 1
View file @ db811f3a
......@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
......
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
+ 1
− 0
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hdl_lib_name = ip_arria10_e2sg_altera_remote_update_1910
# Note, this library causes modelsim to crash!
hdl_library_clause_name = altera_remote_update_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_core_1910
......
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+ 1
− 1
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......@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
......
libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+ 2
− 5
View file @ db811f3a
......@@ -26,10 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
vlib ./work/ ;# Assume library work already exist
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
+ 1
− 3
View file @ db811f3a
hdl_lib_name = ip_arria10_e2sg_asmi_parallel
hdl_library_clause_name = ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
# Do not use this simulation library: it causes Modelsim to crash:
#ip_arria10_e2sg_altera_asmi_parallel_1910
hdl_lib_uses_sim = ip_arria10_e2sg_altera_asmi_parallel_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =
......
libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
+ 1
− 3
View file @ db811f3a
hdl_lib_name = ip_arria10_e2sg_remote_update
hdl_library_clause_name = ip_arria10_e2sg_remote_update_altera_remote_update_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
# Do not use this simulation library: it causes Modelsim to crash:
#ip_arria10_e2sg_altera_remote_update_1910
hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =
......
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