Merge branch 'L2SDP-833' into 'master'

Use g_try_xst_restart = FALSE to verify nof_cycles_dly +1 to ensure proper...

Closes L2SDP-833

See merge request desp/hdl!280

applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd

@@ -67,13 +67,18 @@ USE wpfb_lib.wpfb_pkg.ALL;
 USE lofar2_sdp_lib.sdp_pkg.ALL;
 
 ENTITY tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
+  GENERIC (
+    -- Use g_try_xst_restart = TRUE to check hdr_input.integration_interval in sdp_statistics_offload.vhd,
+    -- default use FALSE for shorter simulation
+    g_try_xst_restart : BOOLEAN := FALSE
+  );
 END tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload;
 
 ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
 
   CONSTANT c_sim             : BOOLEAN := TRUE;
-  CONSTANT c_unb_nr          : NATURAL := 2;
-  CONSTANT c_node_nr         : NATURAL := 1;
+  CONSTANT c_unb_nr          : NATURAL := sel_a_b(g_try_xst_restart, 0, 2);
+  CONSTANT c_node_nr         : NATURAL := sel_a_b(g_try_xst_restart, 0, 1);  -- use node > 0 to check nof_cycles_dly in sdp_statistics_offload.vhd
   CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8);  -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8
   CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
   CONSTANT c_fw_version      : t_unb2c_board_fw_version := (1, 0);
@@ -318,6 +323,27 @@ BEGIN
     -- wait for udp offload is done
     proc_common_wait_until_high(ext_clk, eth_done);
 
+    ----------------------------------------------------------------------------
+    -- XST processing re-enable
+    ----------------------------------------------------------------------------
+    IF g_try_xst_restart THEN
+      -- XST processing disable
+      mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 0, tb_clk);
+      proc_common_wait_some_cycles(ext_clk, c_nof_clk_per_sync/2);
+
+      -- Read current BSN
+      mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+      mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+      proc_common_wait_some_cycles(tb_clk, 1);
+
+      -- XST processing enable
+      v_bsn := TO_UINT(current_bsn_wg) + 7;
+      mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, v_bsn, tb_clk);  -- first write bsn low then bsn high part
+      mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);  -- bsn high, assume v_bsn < 2**31-1
+      mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
+      proc_common_wait_some_cycles(ext_clk, c_nof_clk_per_sync * 4);
+    END IF;
+
     ---------------------------------------------------------------------------
     -- End Simulation 
     ---------------------------------------------------------------------------  

applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt

+Detailed design: Transient Buffer function (LIFT)
+
+
+1) DDR4 memory per receiver input
+
+Bottom up:
+
+Per FPGA there are S_pn = 12 receiver inputs.
+Per FPGA there are N_ddr = 2 DDR4 modules of V_ddr = 8 GByte each.
+==> Per recveiver input N_ddr * V_ddr / S_pn = 1.33 GByte.
+The receiver input data rate is f_adc = 200 MHz and sample width is W_adc = 14 b.
+Assume the samples are stored in 16 b (= 2 bytes), this creates 16/14 = 14 % storage overhead
+Assume 4 % storage overhead for packet header information
+==> Per recveiver input T_tbuf = 1.33 GByte / (2 byte/sample) / 1.04 / f_adc = 3.2 sec maximum storage time.
+==> 192 * 1.33 = 256 GByte / LB for T_tbuf = 3.2 s
+
+Hoe streng is de 3.33 s, mag 3.2 s ook ?
+Moeten we nog grotere 16 GByte modules gaan aanschaffen en te testen met unb2c, zodat we 2x zoveel storage tijd hebben ?
+

applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd

@@ -339,6 +339,10 @@ BEGIN
   -- . O_rn is first GN index in ring, so O_rn <= gn_index
   -- . c_sdp_offload_time = 600000 * 5 ns = 3 ms, so for max gn_index = 31 the
   --   offload starts after 93 ms, to just fit within XST T_int min is 100 ms.
+  -- . use +1 for nof_cycles_dly to ensure that hdr_input.integration_interval gets the correct
+  --   value also for node 0 with zero delay. Otherwise node 0 will read an integration_interval
+  --   value that depends on when the remaining sop_cnt of the last interval in case of a XST
+  --   processing restart.
   p_reg_parameters : PROCESS(dp_clk)
   BEGIN
     IF rising_edge(dp_clk) THEN
@@ -347,7 +351,7 @@ BEGIN
       p.offset_rn        <= TO_UINT(ring_info.O_rn);
       p.rn_index         <= p.gn_index - p.offset_rn;
       p.local_si_offset  <= p.pn_index * c_sdp_S_pn;
-      p.nof_cycles_dly   <= p.gn_index * g_offload_time;
+      p.nof_cycles_dly   <= p.gn_index * g_offload_time + 1;  -- +1 to ensure proper hdr_input.integration_interval also on node 0
       p.nof_rn           <= TO_UINT(ring_info.N_rn);
       p.nof_used_P_sq    <= smallest(p.nof_rn / 2 + 1, g_P_sq);
       p.remote_rn        <= func_ring_nof_hops_to_source_rn(r.instance_count, p.rn_index, p.nof_rn, g_crosslets_direction);