-Completed first test bench + Python test case for correlator.vhd:

 . Only the permutator and the multiplier stages are used
 . Block gens generate subband data from HEX files
   . Single amplitude
   . Phase offset 1 degree per incremental input
   . 1024 identical subbands per stream
 . Correlator multiplies using conjugate so we can extract the phase diffs
 . Data buffers are read out by tc_correlator.py 
   . Phase info is extracted and plotted
 . Current nof_inputs = 24.

libraries/dsp/correlator/src/python/gen_hex_files_complex_subbands.py

+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+from common import *
+from common_dsp import *
+from mem_init_file import list_to_hex
+
+# Purpose:
+# . Generate the NOF_INPUTS complex subband HEX files for the block generators.
+# Description:
+# . 
+
+NOF_INPUTS = 24
+COMPLEX_WIDTH = 16
+NOF_SAMPLES_PER_BLOCK = 1024
+
+AMPLITUDE = pow(2, COMPLEX_WIDTH/2)-1 # Half of the max
+PHASE_SHIFT = 1
+
+MEM_WIDTH  = COMPLEX_WIDTH*2
+MEM_DEPTH  = NOF_SAMPLES_PER_BLOCK
+
+PATH = "../hex"
+FILENAME = "complex_subbands"
+
+# ====================================
+# Create the lists of complex subbands
+# ====================================
+input_list_one_sample = gen_complex_binomials(NOF_INPUTS, AMPLITUDE, PHASE_SHIFT)
+
+input_lists = []
+for input_nr in range(NOF_INPUTS):
+    input_lists.append( NOF_SAMPLES_PER_BLOCK*[input_list_one_sample[input_nr]] )
+
+# =============================================
+# Convert complex type to concatenated unsigned
+# =============================================
+for input_nr in range(NOF_INPUTS):
+    for sample in range(NOF_SAMPLES_PER_BLOCK):
+        re = int(round(input_lists[input_nr][sample].real))
+        im = int(round(input_lists[input_nr][sample].imag))
+        re_bits = CommonBits(re, COMPLEX_WIDTH)
+        im_bits = CommonBits(im, COMPLEX_WIDTH)
+        concat_bits = re_bits & im_bits
+        input_lists[input_nr][sample] = concat_bits.data
+
+# ====================
+# Write the HEX files
+# ====================
+for input_nr in range(NOF_INPUTS):
+    list_to_hex( input_lists[input_nr], PATH+"/"+FILENAME+"_"+str(COMPLEX_WIDTH)+'_'+str(input_nr)+".hex", MEM_WIDTH, MEM_DEPTH)
+

libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd

@@ -30,6 +30,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 -- Description:
 -- . A RAM-block is used to store the running sums as wel as to output the
 --   corresponding previous running sum so both align at the adder inputs.
+-- . g_accumulator_depth=0 connects the source to the sink.
 
 ENTITY corr_accumulator IS
   GENERIC (
@@ -52,77 +53,84 @@ ARCHITECTURE rtl OF corr_accumulator IS
 
   -- c_shiftram_delay is such that common_shiftram output aligns exactly with snk_in_arr. Functionally this 
   -- means we aligned the current word to the corresponding previous word at the adder inputs.
-  CONSTANT c_shiftram_delay           : NATURAL := g_accumulator_depth-c_shiftram_io_delay;
-  CONSTANT c_shift_w                  : NATURAL := ceil_log2(g_accumulator_depth);
-  CONSTANT c_common_shiftram_shift_in : STD_LOGIC_VECTOR(c_shift_w-1 DOWNTO 0) := TO_UVEC(c_shiftram_delay, c_shift_w);
-
-  SIGNAL corr_adder_snk_in_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0); -- Array of pairs
-  SIGNAL corr_adder_src_out_arr       : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
-
-  SIGNAL common_shiftram_snk_in_arr   : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
-  SIGNAL common_shiftram_src_out_arr  : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+--  CONSTANT c_shiftram_delay           : NATURAL := sel_a_b(g_accumulator_depth>0, g_accumulator_depth-c_shiftram_io_delay, 1);
+--  CONSTANT c_shift_w                  : NATURAL := sel_a_b(g_accumulator_depth>0, ceil_log2(g_accumulator_depth), 3);
+--  CONSTANT c_common_shiftram_shift_in : STD_LOGIC_VECTOR(c_shift_w-1 DOWNTO 0) := TO_UVEC(c_shiftram_delay, c_shift_w);
+--
+--  SIGNAL corr_adder_snk_in_2arr_2     : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0); -- Array of pairs
+--  SIGNAL corr_adder_src_out_arr       : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+--
+--  SIGNAL common_shiftram_snk_in_arr   : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+--  SIGNAL common_shiftram_src_out_arr  : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
 
 BEGIN
 
-  -----------------------------------------------------------------------------
-  -- Adder inputs: current snk_in_arr + corresponding previous running sum
-  -- from shiftram
-  -----------------------------------------------------------------------------
-  gen_adder_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-    corr_adder_snk_in_2arr_2(i)(0) <= snk_in_arr(i);
-    corr_adder_snk_in_2arr_2(i)(1) <= common_shiftram_src_out_arr(i);
-  END GENERATE;
-
-  -----------------------------------------------------------------------------
-  -- Complex adder stage
-  -----------------------------------------------------------------------------
-  u_corr_adder : ENTITY work.corr_adder
-  GENERIC MAP (
-    g_nof_inputs => g_nof_inputs
-  )
-  PORT MAP (
-    clk            => clk,
-    rst            => rst,
-
-    snk_in_2arr_2  => corr_adder_snk_in_2arr_2,
-    src_out_arr    => corr_adder_src_out_arr
-  );  
-
-  -----------------------------------------------------------------------------
-  -- Write the current sum to RAM; RAM outputs delayed running sums that align
-  -- at the adder inputs:
-  -- . common_shiftram_src_out_arr = delayed corr_adder_src_out_arr
-  -----------------------------------------------------------------------------
-  -- Concatenate real&imaginary parts
-  gen_concat_complex : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-    common_shiftram_snk_in_arr(i).data(g_data_w-1   DOWNTO g_data_w/2) <= corr_adder_src_out_arr(i).re(g_data_w/2-1 DOWNTO 0);
-    common_shiftram_snk_in_arr(i).data(g_data_w/2-1 DOWNTO 0)          <= corr_adder_src_out_arr(i).im(g_data_w/2-1 DOWNTO 0);
-  END GENERATE;
-
-  gen_common_shiftram : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-    u_common_shiftram : ENTITY common_lib.common_shiftram
-    GENERIC MAP (
-      g_data_w    => g_data_w,
-      g_nof_words => g_accumulator_depth
-    )
-    PORT MAP (
-      rst            => rst,
-      clk            => clk,
-      
-      data_in        => common_shiftram_snk_in_arr(i).data(g_data_w-1 DOWNTO 0),
-      data_in_val    => common_shiftram_snk_in_arr(i).valid,
-      data_in_shift  => c_common_shiftram_shift_in,
-   
-      data_out       => common_shiftram_src_out_arr(i).data(g_data_w-1 DOWNTO 0),
-      data_out_val   => common_shiftram_src_out_arr(i).valid,
-      data_out_shift => OPEN
-    );
+--  gen_accumulator: IF g_accumulator_depth>0 GENERATE
+--    -----------------------------------------------------------------------------
+--    -- Adder inputs: current snk_in_arr + corresponding previous running sum
+--    -- from shiftram
+--    -----------------------------------------------------------------------------
+--    gen_adder_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+--      corr_adder_snk_in_2arr_2(i)(0) <= snk_in_arr(i);
+--      corr_adder_snk_in_2arr_2(i)(1) <= common_shiftram_src_out_arr(i);
+--    END GENERATE;
+--  
+--    -----------------------------------------------------------------------------
+--    -- Complex adder stage
+--    -----------------------------------------------------------------------------
+--    u_corr_adder : ENTITY work.corr_adder
+--    GENERIC MAP (
+--      g_nof_inputs => g_nof_inputs
+--    )
+--    PORT MAP (
+--      clk            => clk,
+--      rst            => rst,
+--  
+--      snk_in_2arr_2  => corr_adder_snk_in_2arr_2,
+--      src_out_arr    => corr_adder_src_out_arr
+--    );  
+--  
+--    -----------------------------------------------------------------------------
+--    -- Write the current sum to RAM; RAM outputs delayed running sums that align
+--    -- at the adder inputs:
+--    -- . common_shiftram_src_out_arr = delayed corr_adder_src_out_arr
+--    -----------------------------------------------------------------------------
+--    -- Concatenate real&imaginary parts
+--    gen_concat_complex : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+--      common_shiftram_snk_in_arr(i).data(g_data_w-1   DOWNTO g_data_w/2) <= corr_adder_src_out_arr(i).re(g_data_w/2-1 DOWNTO 0);
+--      common_shiftram_snk_in_arr(i).data(g_data_w/2-1 DOWNTO 0)          <= corr_adder_src_out_arr(i).im(g_data_w/2-1 DOWNTO 0);
+--    END GENERATE;
+--  
+--    gen_common_shiftram : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+--      u_common_shiftram : ENTITY common_lib.common_shiftram
+--      GENERIC MAP (
+--        g_data_w    => g_data_w,
+--        g_nof_words => g_accumulator_depth
+--      )
+--      PORT MAP (
+--        rst            => rst,
+--        clk            => clk,
+--        
+--        data_in        => common_shiftram_snk_in_arr(i).data(g_data_w-1 DOWNTO 0),
+--        data_in_val    => common_shiftram_snk_in_arr(i).valid,
+--        data_in_shift  => c_common_shiftram_shift_in,
+--     
+--        data_out       => common_shiftram_src_out_arr(i).data(g_data_w-1 DOWNTO 0),
+--        data_out_val   => common_shiftram_src_out_arr(i).valid,
+--        data_out_shift => OPEN
+--      );
+--    END GENERATE;
+--  
+--    -----------------------------------------------------------------------------
+--    -- Output 1/g_accumulator_depth words per stream
+--    -- . Not implemented yet.
+--    -----------------------------------------------------------------------------
+--    src_out_arr <= common_shiftram_src_out_arr;
+--
+--  END GENERATE;
+--
+  gen_bypass: IF g_accumulator_depth<1 GENERATE
+    src_out_arr <= snk_in_arr;
   END GENERATE;
 
-  -----------------------------------------------------------------------------
-  -- Output 1/g_accumulator_depth words per stream
-  -- . Not implemented yet.
-  -----------------------------------------------------------------------------
-  src_out_arr <= common_shiftram_src_out_arr;
-
 END rtl;

libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd

@@ -33,7 +33,9 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY corr_multiplier IS
   GENERIC (
-    g_nof_inputs  : NATURAL
+    g_nof_inputs  : NATURAL;
+    g_data_w      : NATURAL;
+    g_conjugate   : BOOLEAN -- Take conjugate of snk_in_2arr_2[i][1]
    ); 
   PORT (
     rst            : IN  STD_LOGIC;
@@ -57,10 +59,10 @@ BEGIN
     --u_dut : ENTITY work.common_complex_mult(stratix4)
     --u_dut : ENTITY work.common_complex_mult(str_stratix4)
     GENERIC MAP (
-      g_in_a_w           => 18,
-      g_in_b_w           => 18,
-      g_out_p_w          => 36,     -- default use g_out_p_w = g_in_a_w+g_in_b_w
-      g_conjugate_b      => FALSE,
+      g_in_a_w           => g_data_w,
+      g_in_b_w           => g_data_w,
+      g_out_p_w          => 2*g_data_w,     -- default use g_out_p_w = g_in_a_w+g_in_b_w
+      g_conjugate_b      => g_conjugate,
       g_pipeline_input   => 1,
       g_pipeline_product => 0,
       g_pipeline_adder   => 1,
@@ -69,12 +71,15 @@ BEGIN
     PORT MAP (
       clk        => clk,
       clken      => '1',
-      in_ar      => snk_in_2arr_2(i)(0).re(17 DOWNTO 0),
-      in_ai      => snk_in_2arr_2(i)(0).im(17 DOWNTO 0),
-      in_br      => snk_in_2arr_2(i)(1).re(17 DOWNTO 0),
-      in_bi      => snk_in_2arr_2(i)(1).im(17 DOWNTO 0),
-      out_pr     => src_out_arr(i).re(35 DOWNTO 0),
-      out_pi     => src_out_arr(i).im(35 DOWNTO 0)
+      rst        => rst,
+      in_ar      => snk_in_2arr_2(i)(0).re(g_data_w-1 DOWNTO 0),
+      in_ai      => snk_in_2arr_2(i)(0).im(g_data_w-1 DOWNTO 0),
+      in_br      => snk_in_2arr_2(i)(1).re(g_data_w-1 DOWNTO 0),
+      in_bi      => snk_in_2arr_2(i)(1).im(g_data_w-1 DOWNTO 0),
+      in_val     => snk_in_2arr_2(i)(0).valid,
+      out_pr     => src_out_arr(i).re(2*g_data_w-1 DOWNTO 0),
+      out_pi     => src_out_arr(i).im(2*g_data_w-1 DOWNTO 0),
+      out_val    => src_out_arr(i).valid
     );     
   END GENERATE;
 

libraries/dsp/correlator/src/vhdl/correlator.vhd

@@ -33,7 +33,9 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY correlator IS
   GENERIC (
     g_nof_inputs  : NATURAL;
-    g_nof_mults   : NATURAL
+    g_nof_mults   : NATURAL;
+    g_data_w      : NATURAL := 16;
+    g_conjugate   : BOOLEAN := TRUE
    ); 
   PORT (
     rst            : IN  STD_LOGIC;
@@ -41,7 +43,7 @@ ENTITY correlator IS
 
     snk_in_arr     : IN  t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
 
-    src_out        : OUT t_dp_sosi
+    src_out_arr    : OUT t_dp_sosi_arr(g_nof_inputs*(g_nof_inputs+1)/2-1 DOWNTO 0)
   );
 END correlator;
 
@@ -80,7 +82,9 @@ BEGIN
   -----------------------------------------------------------------------------
   u_corr_multiplier : ENTITY work.corr_multiplier
   GENERIC MAP (
-    g_nof_inputs => g_nof_mults
+    g_nof_inputs => g_nof_mults,
+    g_data_w     => g_data_w,
+    g_conjugate  => g_conjugate
   )
   PORT MAP (
     clk            => clk,
@@ -96,7 +100,7 @@ BEGIN
   u_corr_accumulator : ENTITY work.corr_accumulator
   GENERIC MAP (
     g_nof_inputs        => g_nof_mults,
-    g_accumulator_depth => 10,
+    g_accumulator_depth => 0,
     g_data_w            => 64
   )
   PORT MAP (
@@ -107,4 +111,6 @@ BEGIN
     src_out_arr    => corr_accumulator_src_out_arr
   );
 
+  src_out_arr <= corr_accumulator_src_out_arr;
+
 END str;

libraries/dsp/correlator/tb/python/tc_correlator.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Purpose:
+# Description:
+# Usage:
+
+COMPLEX_WIDTH = 16
+NOF_INPUTS = 24
+NOF_OUTPUTS = NOF_INPUTS*(NOF_INPUTS+1)/2
+
+NOF_DUMMY_VISIBILITIES = NOF_INPUTS*NOF_INPUTS-NOF_OUTPUTS
+DUMMY_VISIBILITIES = NOF_DUMMY_VISIBILITIES*[0.0]
+
+BUFFER_DEPTH = 1024
+BUFFER_WIDTH = 2*COMPLEX_WIDTH
+
+from common import *
+from common_dsp import *
+
+import test_case
+import node_io
+import pi_diag_data_buffer
+
+tc = test_case.Testcase('TB - ', '')
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=NOF_OUTPUTS, ramSizePerStream=BUFFER_DEPTH)
+
+###############################################################################
+# Read the first word from each data buffer (all words per stream are the same)
+###############################################################################
+data = []
+for output_nr in range(NOF_OUTPUTS):
+    data.append( db.read_data_buffer(streamNr=output_nr, n=1, radix='dec', width=BUFFER_WIDTH, nofColumns=12) )
+
+###############################################################################
+# Convert the unsigned words to complex
+###############################################################################
+data = flatten(data)
+for index,word in enumerate(data):
+    word_bits = CommonBits(word, BUFFER_WIDTH)
+    re = word_bits[BUFFER_WIDTH-1:COMPLEX_WIDTH]
+    im = word_bits[COMPLEX_WIDTH-1:0]
+    data[index] = complex(im, re)
+
+###############################################################################
+# Convert binomials to complex phasor notation
+###############################################################################
+for index,word in enumerate(data):
+    data[index] = complex_binomial_to_phasor(word)
+
+###############################################################################
+# Extract the phases from the complex data
+###############################################################################
+phases = []
+for word in data:
+    phases.append(word[1])
+
+################################################################################
+# Re-shape the flat list into a matrix and plot it
+################################################################################
+mat = unique_vis_to_full_matrix(phases)
+plot_matrix_color([[mat]])

libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd

@@ -19,30 +19,71 @@
 --
 --------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, mm_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
 
 ENTITY tb_correlator IS
 END tb_correlator;
 
 ARCHITECTURE tb OF tb_correlator IS
 
-  CONSTANT c_nof_inputs         : NATURAL := 4;
+  CONSTANT c_nof_inputs         : NATURAL := 24;
   CONSTANT c_nof_mults          : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
 
   CONSTANT c_clk_period         : TIME := 10 ns;
   CONSTANT c_data_w             : NATURAL := 32;
 
+  -- Block generator
+  CONSTANT c_bg_block_size              : NATURAL := 1024;
+  CONSTANT c_bg_gapsize                 : NATURAL := 0;
+  CONSTANT c_bg_blocks_per_sync         : NATURAL := 10;
+  CONSTANT c_bg_ctrl                    : t_diag_block_gen := ('1',                      -- enable             
+                                                               '0',                      -- enable_sync        
+                                                              TO_UVEC(     c_bg_block_size, c_diag_bg_samples_per_packet_w),
+                                                              TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+                                                              TO_UVEC(        c_bg_gapsize, c_diag_bg_gapsize_w),
+                                                              TO_UVEC(                   0, c_diag_bg_mem_low_adrs_w),
+                                                              TO_UVEC(   c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+                                                              TO_UVEC(                   0, c_diag_bg_bsn_init_w));
+
+
   SIGNAL tb_end                 : STD_LOGIC := '0';
   SIGNAL clk                    : STD_LOGIC := '1';
   SIGNAL rst                    : STD_LOGIC;
 
   SIGNAL correlator_snk_in_arr  : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
-  SIGNAL correlator_src_out     : t_dp_sosi;
+  SIGNAL correlator_src_out_arr : t_dp_sosi_arr(c_nof_inputs*(c_nof_inputs+1)/2-1 DOWNTO 0);
+
+  SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
+  SIGNAL ram_diag_data_buf_miso : t_mem_miso;
+  SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
+  SIGNAL reg_diag_data_buf_miso : t_mem_miso; 
+
+  ----------------------------------------------------------------------------
+  -- mm_file component
+  ----------------------------------------------------------------------------
+  COMPONENT mm_file
+  GENERIC(
+    g_file_prefix       : STRING;
+    g_mm_clk_period     : TIME := c_clk_period;
+    g_update_on_change  : BOOLEAN := FALSE;
+    g_mm_rd_latency     : NATURAL := 1
+  );
+  PORT (
+    mm_rst        : IN  STD_LOGIC;
+    mm_clk        : IN  STD_LOGIC;
+    mm_master_out : OUT t_mem_mosi;
+    mm_master_in  : IN  t_mem_miso 
+  );
+  END COMPONENT;
 
 BEGIN
 
@@ -53,9 +94,29 @@ BEGIN
   rst <= '1', '0' AFTER c_clk_period*7;
 
   -----------------------------------------------------------------------------
-  -- Test data
+  -- Block generators
+  -- . Each stream in block_gen_src_out_arr contains complex subband samples
+  --   from one 'antenna'.
+  -- . These complex subband samples are generated and converted to a HEX RAM
+  --   initialization file using Python, see tb/python/gen_subband_hex_files.py
   -----------------------------------------------------------------------------
+  u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+  GENERIC MAP (
+    g_nof_output_streams => c_nof_inputs,
+    g_buf_dat_w          => c_data_w,
+    g_buf_addr_w         => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+    g_file_name_prefix   => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & NATURAL'IMAGE(c_data_w/2),
+    g_diag_block_gen_rst => c_bg_ctrl
+  )
+  PORT MAP (
+    mm_rst           => rst,
+    mm_clk           => clk,
+
+    dp_rst           => rst,
+    dp_clk           => clk,
 
+    out_sosi_arr     => correlator_snk_in_arr
+  );
 
   -----------------------------------------------------------------------------
   -- Device under test: correlator
@@ -70,7 +131,47 @@ BEGIN
     rst         => rst,
 
     snk_in_arr  => correlator_snk_in_arr,
-    src_out     => correlator_src_out
+    src_out_arr => correlator_src_out_arr
   );
 
+  -----------------------------------------------------------------------------
+  -- Data buffers to be read out by Python
+  -----------------------------------------------------------------------------
+  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (    
+    g_nof_streams  => c_nof_mults,
+    g_data_w       => c_data_w,
+    g_data_type    => e_complex,
+    g_buf_nof_data => c_bg_block_size,
+    g_buf_use_sync => FALSE 
+  )
+  PORT MAP (
+    mm_rst            => rst,
+    mm_clk            => clk,
+    dp_rst            => rst,
+    dp_clk            => clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_miso,
+
+    in_sosi_arr       => correlator_src_out_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- MM file I/O with Python
+  -----------------------------------------------------------------------------
+  u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
+                                              PORT MAP(rst, clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+  u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
+                                              PORT MAP(rst, clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
+  ----------------------------------------------------------------------------
+  -- Procedure that polls a sim control file that can be used to e.g. get
+  -- the simulation time in ns
+  ----------------------------------------------------------------------------
+  mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
 END tb;