Merge branch 'L2SDP-390' into 'master'

Corrected c_block_size_w, by using +1 to ensure that g_block_size that is...

Closes L2SDP-390

See merge request desp/hdl!254

applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd

@@ -146,7 +146,7 @@ ENTITY tb_lofar2_unb2c_sdp_station_bf IS
     g_sp_remnant_ampl    : REAL := 0.1;       -- WG normalized amplitude for remnant sp
     g_sp_remnant_phase   : REAL := 15.0;      -- WG phase in degrees for remnant sp
     g_subband            : NATURAL := 102;    -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
-    g_beamlet            : NATURAL := 10;     -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+    g_beamlet            : NATURAL := c_sdp_S_sub_bf-1;     -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
     g_beamlet_scale      : REAL := 1.0 / 2.0**9;  -- g_beamlet output scale factor
     g_bf_x_gain          : REAL := 0.7;       -- g_beamlet X BF weight normalized gain for g_sp
     g_bf_y_gain          : REAL := 0.6;       -- g_beamlet Y BF weight normalized gain for g_sp
@@ -156,8 +156,8 @@ ENTITY tb_lofar2_unb2c_sdp_station_bf IS
     g_bf_remnant_y_gain  : REAL := 0.04;       -- g_beamlet Y BF weight normalized gain for remnant sp
     g_bf_remnant_x_phase : REAL := 170.0;       -- g_beamlet X BF weight phase rotation in degrees for g_sp
     g_bf_remnant_y_phase : REAL := -135.0;       -- g_beamlet Y BF weight phase rotation in degrees for g_sp
-    g_read_all_SST       : BOOLEAN := FALSE;  -- when FALSE only read SST for g_subband, to save sim time
-    g_read_all_BST       : BOOLEAN := FALSE   -- when FALSE only read BST for g_beamlet, to save sim time
+    g_read_all_SST       : BOOLEAN := TRUE;  -- when FALSE only read SST for g_subband, to save sim time
+    g_read_all_BST       : BOOLEAN := TRUE   -- when FALSE only read BST for g_beamlet, to save sim time
   );
 END tb_lofar2_unb2c_sdp_station_bf;
 
@@ -333,6 +333,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
   CONSTANT c_addr_w_ram_bf_weights        : NATURAL := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
   CONSTANT c_addr_w_reg_bf_scale          : NATURAL := 1;
   CONSTANT c_addr_w_reg_hdr_dat           : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+  CONSTANT c_addr_w_reg_stat_enable_bst   : NATURAL := c_sdp_reg_stat_enable_addr_w;
   CONSTANT c_addr_w_reg_dp_xonoff         : NATURAL := 1;
   CONSTANT c_addr_w_ram_st_bst            : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*c_stat_data_sz);
   -- . Address spans of a single MM instance
@@ -343,6 +344,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
   CONSTANT c_mm_span_ram_bf_weights       : NATURAL := 2**c_addr_w_ram_bf_weights;
   CONSTANT c_mm_span_reg_bf_scale         : NATURAL := 2**c_addr_w_reg_bf_scale;
   CONSTANT c_mm_span_reg_hdr_dat          : NATURAL := 2**c_addr_w_reg_hdr_dat;
+  CONSTANT c_mm_span_reg_stat_enable_bst  : NATURAL := 2**c_addr_w_reg_stat_enable_bst;
   CONSTANT c_mm_span_reg_dp_xonoff        : NATURAL := 2**c_addr_w_reg_dp_xonoff;
   CONSTANT c_mm_span_ram_st_bst           : NATURAL := 2**c_addr_w_ram_st_bst;
 
@@ -354,7 +356,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
   CONSTANT c_mm_file_reg_dp_selector      : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_SELECTOR";
   CONSTANT c_mm_file_ram_st_sst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
   CONSTANT c_mm_file_ram_st_bst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_BST";
-  CONSTANT c_mm_file_reg_dp_xonoff        : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";
+  CONSTANT c_mm_file_reg_stat_enable_bst  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST";  -- BST offload enable
+  CONSTANT c_mm_file_reg_dp_xonoff        : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";  -- beamlet output enable
   CONSTANT c_mm_file_ram_ss_ss_wide       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_SS_SS_WIDE";
   CONSTANT c_mm_file_ram_bf_weights       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BF_WEIGHTS";
   CONSTANT c_mm_file_reg_bf_scale         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
@@ -779,7 +782,13 @@ BEGIN
       ASSERT rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port REPORT "Wrong MM read rd_cep_udp_dst_port for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR;  -- 5000
 
       ----------------------------------------------------------------------------
-      -- Enable beamlet UDP offload (dp_xonoff)
+      -- Enable BST offload (not verified here, but only for view in Wave window)
+      ----------------------------------------------------------------------------
+      v_offset := bset * c_mm_span_reg_stat_enable_bst;
+      mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst, v_offset + 0, 1, tb_clk);
+
+      ----------------------------------------------------------------------------
+      -- Enable beamlet output (dp_xonoff)
       ----------------------------------------------------------------------------
       v_offset := bset * c_mm_span_reg_dp_xonoff;
       mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff, v_offset + 0, 1, tb_clk);

applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd

@@ -48,7 +48,7 @@ BEGIN
     g_sp_remnant_ampl    => 0.1,           -- WG normalized amplitude for remnant sp
     g_sp_remnant_phase   => 15.0,          -- WG phase in degrees for remnant sp
     g_subband            => 102,           -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
-    g_beamlet            => 10,            -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+    g_beamlet            => c_sdp_S_sub_bf-1,  -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
     g_beamlet_scale      => 1.0 / 2.0**9,  -- g_beamlet output scale factor
     g_bf_x_gain          => 0.7,           -- g_beamlet X BF weight normalized gain for g_sp
     g_bf_y_gain          => 0.6,           -- g_beamlet Y BF weight normalized gain for g_sp

applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd

@@ -114,8 +114,7 @@
 --     sim:/tb_lofar2_unb2c_sdp_station_bf_ring/sp_ssts_arr2 \
 --     sim:/tb_lofar2_unb2c_sdp_station_bf_ring/bsts_arr2
 --   > run -a  
---   Takes about   40 m when g_read_all_* = FALSE
---   Takes about 1h 5 m when g_read_all_* = TRUE
+--   Takes about 1h 58m when g_read_all_* = FALSE
 --
 -------------------------------------------------------------------------------
 LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
@@ -146,7 +145,7 @@ ENTITY tb_lofar2_unb2c_sdp_station_bf_ring IS
     g_sp_remnant_ampl    : REAL := 0.1;       -- WG normalized amplitude for remnant sp
     g_sp_remnant_phase   : REAL := 15.0;      -- WG phase in degrees for remnant sp
     g_subband            : NATURAL := 102;    -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
-    g_beamlet            : NATURAL := 10;     -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+    g_beamlet            : NATURAL := c_sdp_S_sub_bf-1;     -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
     g_beamlet_scale      : REAL := 1.0 / 2.0**9;  -- g_beamlet output scale factor
     g_bf_x_gain          : REAL := 0.7;       -- g_beamlet X BF weight normalized gain for g_sp
     g_bf_y_gain          : REAL := 0.6;       -- g_beamlet Y BF weight normalized gain for g_sp
@@ -167,7 +166,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
   CONSTANT c_unb_nr              : NATURAL := 0; -- UniBoard 0
   CONSTANT c_node_nr             : NATURAL := 0;
   CONSTANT c_nof_rn              : NATURAL := 2;
-  CONSTANT c_gn_index            : NATURAL := c_unb_nr * 4 + c_nof_rn-1; -- end node GN
+  CONSTANT c_last_unb_nr         : NATURAL := (c_nof_rn-1) / c_quad;
+  CONSTANT c_last_rn_nr          : NATURAL := c_nof_rn-1;
+  CONSTANT c_gn_index            : NATURAL := c_unb_nr * c_quad + c_nof_rn-1; -- end node GN
   CONSTANT c_init_bsn            : NATURAL := 17;  -- some recognizable value >= 0
   CONSTANT c_nof_lanes           : NATURAL := c_sdp_N_beamsets;
 
@@ -175,8 +176,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
   CONSTANT c_version             : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
   CONSTANT c_fw_version          : t_unb2c_board_fw_version := (1, 0);
 
-  CONSTANT c_mac_15_0            : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + ((c_nof_rn-1) / c_quad), 8) & TO_UVEC((c_nof_rn-1) MOD c_quad, 8);
-  CONSTANT c_ip_15_0             : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + ((c_nof_rn-1) / c_quad), 8) & TO_UVEC(((c_nof_rn-1) MOD c_quad) +1, 8);  -- +1 to avoid IP = *.*.*.0
+  CONSTANT c_mac_15_0            : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + c_last_unb_nr, 8) & TO_UVEC(c_last_rn_nr MOD c_quad, 8);
+  CONSTANT c_ip_15_0             : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + c_last_unb_nr, 8) & TO_UVEC((c_last_rn_nr MOD c_quad) +1, 8);  -- +1 to avoid IP = *.*.*.0
 
   CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
   CONSTANT c_ext_clk_period      : TIME := 5 ns;
@@ -335,6 +336,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
   CONSTANT c_addr_w_ram_bf_weights        : NATURAL := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
   CONSTANT c_addr_w_reg_bf_scale          : NATURAL := 1;
   CONSTANT c_addr_w_reg_hdr_dat           : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+  CONSTANT c_addr_w_reg_stat_enable_bst   : NATURAL := c_sdp_reg_stat_enable_addr_w;
   CONSTANT c_addr_w_reg_dp_xonoff         : NATURAL := 1;
   CONSTANT c_addr_w_ram_st_bst            : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*c_stat_data_sz);
   -- . Address spans of a single MM instance
@@ -345,6 +347,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
   CONSTANT c_mm_span_ram_bf_weights       : NATURAL := 2**c_addr_w_ram_bf_weights;
   CONSTANT c_mm_span_reg_bf_scale         : NATURAL := 2**c_addr_w_reg_bf_scale;
   CONSTANT c_mm_span_reg_hdr_dat          : NATURAL := 2**c_addr_w_reg_hdr_dat;
+  CONSTANT c_mm_span_reg_stat_enable_bst  : NATURAL := 2**c_addr_w_reg_stat_enable_bst;
   CONSTANT c_mm_span_reg_dp_xonoff        : NATURAL := 2**c_addr_w_reg_dp_xonoff;
   CONSTANT c_mm_span_ram_st_bst           : NATURAL := 2**c_addr_w_ram_st_bst;
 
@@ -355,8 +358,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
   CONSTANT c_mm_file_ram_equalizer_gains  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_EQUALIZER_GAINS";
   CONSTANT c_mm_file_reg_dp_selector      : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_SELECTOR";
   CONSTANT c_mm_file_ram_st_sst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
-  CONSTANT c_mm_file_ram_st_bst           : STRING := mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "RAM_ST_BST"; --end RN
-  CONSTANT c_mm_file_reg_dp_xonoff        : STRING := mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_DP_XONOFF"; --end RN
+  CONSTANT c_mm_file_ram_st_bst           : STRING := mmf_unb_file_prefix(c_unb_nr + c_last_unb_nr, c_last_rn_nr MOD c_quad) & "RAM_ST_BST"; --end RN
+  CONSTANT c_mm_file_reg_stat_enable_bst  : STRING := mmf_unb_file_prefix(c_unb_nr + c_last_unb_nr, c_last_rn_nr MOD c_quad) & "REG_STAT_ENABLE_BST"; --end RN
+  CONSTANT c_mm_file_reg_dp_xonoff        : STRING := mmf_unb_file_prefix(c_unb_nr + c_last_unb_nr, c_last_rn_nr MOD c_quad) & "REG_DP_XONOFF"; --end RN
   CONSTANT c_mm_file_ram_ss_ss_wide       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_SS_SS_WIDE";
   CONSTANT c_mm_file_ram_bf_weights       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BF_WEIGHTS";
   CONSTANT c_mm_file_reg_bf_scale         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
@@ -820,7 +824,13 @@ BEGIN
       ASSERT rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port REPORT "Wrong MM read rd_cep_udp_dst_port for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR;  -- 5000
 
       ----------------------------------------------------------------------------
-      -- Enable beamlet UDP offload off end node (dp_xonoff)
+      -- Enable BST offload on end node (not verified here, but only for view in Wave window)
+      ----------------------------------------------------------------------------
+      v_offset := bset * c_mm_span_reg_stat_enable_bst;
+      mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst, v_offset + 0, 1, tb_clk);
+
+      ----------------------------------------------------------------------------
+      -- Enable beamlet output on end node (dp_xonoff)
       ----------------------------------------------------------------------------
       v_offset := bset * c_mm_span_reg_dp_xonoff;
       mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff, v_offset + 0, 1, tb_clk);
@@ -854,8 +864,8 @@ BEGIN
     mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
   
     -- End node specific settings
-    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
-    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + c_last_unb_nr, c_last_rn_nr MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
+    mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + c_last_unb_nr, c_last_rn_nr MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
      
     -- Access scheme 1. Each RN uses and sends them along the ring.
     FOR RN IN 0 TO c_nof_rn-1 LOOP

libraries/base/common/hdllib.cfg

@@ -148,6 +148,7 @@ synth_files =
     tb/vhdl/tb_common_mem_pkg.vhd
     
 test_bench_files = 
+    tb/vhdl/tb_common_log.vhd
     tb/vhdl/tb_common_acapture.vhd
     tb/vhdl/tb_common_add_sub.vhd
     tb/vhdl/tb_common_adder_tree.vhd

libraries/base/common/tb/vhdl/tb_common_log.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, 11 May 2022
+-- Purpose: Show pow and log functions from common_pkg.vhd
+-- Description:
+-- Usage:
+-- > run -all
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.common_pkg.ALL;
+USE work.common_str_pkg.ALL;
+
+ENTITY tb_common_log IS
+END tb_common_log;
+
+ARCHITECTURE tb OF tb_common_log IS
+BEGIN
+
+  p_log : PROCESS
+    CONSTANT c_range : t_integer_arr := (99, 100, 101, 127, 128, 129);
+    VARIABLE vI      : NATURAL;
+  BEGIN
+    print_str("I: pow2, ceil_pow2");
+    FOR I IN 1 TO 20 LOOP
+      print_str(int_to_str(I) & ": " &
+                int_to_str(pow2(I)) & ", " &
+                int_to_str(ceil_pow2(I)));
+    END LOOP;
+    print_str("");
+    print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
+    FOR I IN 1 TO 20 LOOP
+      print_str(int_to_str(I) & ": " &
+                int_to_str(ceil_log2(I)) & ", " &
+                int_to_str(true_log2(I)) & ", " &
+                int_to_str(true_log_pow2(I)) & ", " &
+                bool_to_str(is_pow2(I)) & ", " &
+                int_to_str(floor_log10(I)));
+    END LOOP;
+    print_str("");
+    print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
+    FOR I IN c_range'RANGE LOOP
+      vI := c_range(I);
+      print_str(int_to_str(vI) & ": " &
+                int_to_str(ceil_log2(vI)) & ", " &
+                int_to_str(true_log2(vI)) & ", " &
+                int_to_str(true_log_pow2(vI)) & ", " &
+                bool_to_str(is_pow2(vI)) & ", " &
+                int_to_str(floor_log10(vI)));
+    END LOOP;
+    WAIT;
+  END PROCESS;
+
+END tb;

libraries/base/dp/hdllib.cfg

@@ -424,3 +424,5 @@ regression_test_vhdl =
 
 
 [quartus_project_file]
+quartus_copy_files =
+    $RADIOHDL_WORK/libraries/base/dp/quartus_unb2c  quartus_unb2c

libraries/base/dp/quartus_unb2c/dp_bsn_align_v2.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.4.0 Build 64 12/04/2019 SC Pro Edition
+# Date created = 13:49:06  May 11, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "19.4"
+DATE = "13:49:06  May 11, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "dp_bsn_align_v2"

libraries/base/dp/quartus_unb2c/dp_bsn_align_v2.qsf

+###############################################################################
+# Copyright 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+###############################################################################
+#
+# Author: E. Kooistra, 11 May 2022
+# Purpose: Synthesis of dp_bsn_align_v2 to investigate M20K BRAM usage
+#
+# Description:
+# . Created dp_bsn_align_v2.qpf and qsf with GUI using run_quartus unb2c &
+# . Use virtual pins so that it fits the FPGA, as explained in [1].
+#
+# References:
+# [1] "Virtual Pin Assignments in a Partial Design", Apr 17, 2021,
+#     https://www.youtube.com/watch?v=QET0lC-jdAQ
+
+set_global_assignment -name TOP_LEVEL_ENTITY dp_bsn_align_v2
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.4.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:49:06  MAY 11, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.4.0 Pro Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE 10AX115N2F45E2SG
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Used GUI to add the qip files that dp_bsn_align_v2 depends on:
+set_global_assignment -name QIP_FILE ../../ip_arria10_e2sg_ram/ip_arria10_e2sg_ram_lib.qip
+set_global_assignment -name QIP_FILE ../../tech_mult/tech_mult_lib.qip
+set_global_assignment -name QIP_FILE ../../common_mult/common_mult_lib.qip
+set_global_assignment -name QIP_FILE ../../tech_iobuf/tech_iobuf_lib.qip
+set_global_assignment -name QIP_FILE ../../mm/mm_lib.qip
+set_global_assignment -name QIP_FILE ../../tech_fifo/tech_fifo_lib.qip
+set_global_assignment -name QIP_FILE ../../easics/easics_lib.qip
+set_global_assignment -name QIP_FILE ../../technology/technology_lib.qip
+set_global_assignment -name QIP_FILE ../../tech_memory/tech_memory_lib.qip
+set_global_assignment -name QIP_FILE ../../common/common_lib.qip
+set_global_assignment -name QIP_FILE ../dp_lib.qip
+
+# Used GUI to add the ports of dp_bsn_align_v2 as virtual pins so that it fits the FPGA [1].
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].rdval
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].waitrequest
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].rdval
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].waitrequest
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.rd
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.wr
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.eop
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.sop
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.sync
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].re
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[0].rddata
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_cipo_arr[1].rddata
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.address
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_copi.wrdata
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.channel
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.data
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.empty
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.err
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.im
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_sosi.re
+set_instance_assignment -name VIRTUAL_PIN ON -to node_index
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[0].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_sosi_arr[1].re
+set_instance_assignment -name VIRTUAL_PIN ON -to stream_en_arr
+set_instance_assignment -name VIRTUAL_PIN ON -to stream_replaced_cnt_arr
+set_instance_assignment -name VIRTUAL_PIN ON -to dp_rst

libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd

@@ -57,12 +57,12 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY dp_bsn_align_v2 IS
   GENERIC (
-    g_nof_streams                : NATURAL;           -- >= 2, number of input and output streams
-    g_bsn_latency_max            : NATURAL;           -- maximum travel latency of a remote block in number of block periods T_blk
-    g_nof_aligners_max           : POSITIVE := 1;     -- 1 when only align at last node, > 1 when align at every intermediate node
-    g_block_size                 : NATURAL := 32;     -- > 1, g_block_size=1 is not supported
+    g_nof_streams                : NATURAL := 2;           -- >= 2, number of input and output streams
+    g_bsn_latency_max            : NATURAL := 2;           -- maximum travel latency of a remote block in number of block periods T_blk
+    g_nof_aligners_max           : POSITIVE := 16;     -- 1 when only align at last node, > 1 when align at every intermediate node
+    g_block_size                 : NATURAL := 1024;     -- > 1, g_block_size=1 is not supported
     g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
-    g_data_w                     : NATURAL;           -- number of bits in sosi data
+    g_data_w                     : NATURAL := 36;           -- number of bits in sosi data
     g_data_replacement_value     : INTEGER := 0;      -- output sosi data value for missing input blocks
     g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
     g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
@@ -105,7 +105,8 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
                                           nof_dat  => c_ram_size,
                                           init_sl  => '0');
 
-  CONSTANT c_block_size_w   : NATURAL := ceil_log2(g_block_size);
+  -- Use +1 to ensure that g_block_size that is power of 2 also fits in c_block_size_slv
+  CONSTANT c_block_size_w   : NATURAL := ceil_log2(g_block_size + 1);
   CONSTANT c_block_size_slv : STD_LOGIC_VECTOR(c_block_size_w-1 DOWNTO 0) := TO_UVEC(g_block_size, c_block_size_w);
   CONSTANT c_blk_pointer_w  : NATURAL := ceil_log2(c_buffer_nof_blocks);
 

libraries/base/dp/src/vhdl/dp_field_blk.vhd

@@ -130,7 +130,7 @@ ARCHITECTURE str OF dp_field_blk IS
   CONSTANT c_mm_fields_slv_out_w : NATURAL := sel_a_b(c_field_to_block, g_snk_data_w, 0);
 
   SIGNAL mm_fields_slv_in     : STD_LOGIC_VECTOR(c_mm_fields_slv_in_w-1 DOWNTO 0);
-  SIGNAL mm_fields_slv_in_val : STD_LOGIC;
+  SIGNAL mm_fields_slv_in_val : STD_LOGIC := '0';  -- default '0' when c_field_to_block = TRUE
   SIGNAL mm_fields_slv_out    : STD_LOGIC_VECTOR(c_mm_fields_slv_out_w-1 DOWNTO 0);
 
   SIGNAL field_override_arr : STD_LOGIC_VECTOR(g_field_arr'RANGE) := g_field_sel; --1 override bit per field
@@ -176,7 +176,6 @@ BEGIN
     -- MM readout of fields
     mm_fields_slv_in     <= dp_repack_data_src_out.data(g_src_data_w-1 DOWNTO 0);
     mm_fields_slv_in_val <= dp_repack_data_src_out.valid;
-
   END GENERATE;
 
   ---------------------------------------------------------------------------------------

libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd

@@ -67,9 +67,11 @@ BEGIN
   -- g_tb_nof_blocks        : NATURAL := 10       -- number of input blocks per restart
 
   u_mm_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3,    TRUE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_mm_output_pow2          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1,      16, c_period, 32, 16, 17, 0, 0,  0, 3,    TRUE, 0, 0, 1,  0, 2, c_nof_blk);  -- g_block_size = 2**4 = 16
   u_mm_output_large_bsn     : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3000, TRUE, 0, 0, 1,  0, 2, c_nof_blk);  -- test where bsn * g_block_size > 2^10 to test address resizing
   u_mm_output_single        : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3,    TRUE, 0, 0, 1,  0, 2, c_nof_blk);
   u_dp_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3,    FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_dp_output_pow2          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1,      16, c_period, 32, 16, 17, 0, 0,  0, 3,    FALSE, 0, 0, 1,  0, 2, c_nof_blk);  -- g_block_size = 2**4 = 16
   u_dp_output_large_bsn     : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3000, FALSE, 0, 0, 1,  0, 2, c_nof_blk); -- test where bsn * g_block_size > 2^10 to test address resizing
   u_dp_output_single        : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3,    FALSE, 0, 0, 1,  0, 2, c_nof_blk);
   u_dp_output_p1            : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, 3,    FALSE, 1, 1, 1,  0, 2, c_nof_blk);