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RTSD
HDL
Commits
d7e3a73b
Commit
d7e3a73b
authored
May 17, 2016
by
Eric Kooistra
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Remove note.
parent
92549fbc
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1 changed file
tools/oneclick/base/modelsim_config.py
+0
-7
0 additions, 7 deletions
tools/oneclick/base/modelsim_config.py
with
0 additions
and
7 deletions
tools/oneclick/base/modelsim_config.py
+
0
−
7
View file @
d7e3a73b
...
@@ -374,13 +374,6 @@ if __name__ == '__main__':
...
@@ -374,13 +374,6 @@ if __name__ == '__main__':
for
sim_dir
in
msim
.
get_lib_build_dirs
(
'
sim
'
):
for
sim_dir
in
msim
.
get_lib_build_dirs
(
'
sim
'
):
print
'
'
,
sim_dir
print
'
'
,
sim_dir
if
len
(
msim
.
unavailable_use_libs
)
>
0
or
len
(
msim
.
unavailable_include_ip_libs
)
>
0
:
print
''
print
'
Note: unavailable library names occur when e.g. a technology IP library is not available in the toolRootDir because it is not needed,
'
print
'
or it may indicate a spelling error.
'
print
"
. The following unavailable library names were found at one or more
'
hdl_lib_uses_*
'
key =
"
,
msim
.
unavailable_use_libs
print
"
. The following unavailable library names were found at one or more
'
hdl_lib_include_ip
'
key =
"
,
msim
.
unavailable_include_ip_libs
print
''
print
''
print
'
Create library compile order files for simulation.
'
print
'
Create library compile order files for simulation.
'
msim
.
create_lib_order_files
(
'
sim
'
)
msim
.
create_lib_order_files
(
'
sim
'
)
...
...
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