Connect eth_stream for 1GbE-II.

boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd

@@ -268,15 +268,10 @@ ARCHITECTURE str OF unb2c_test IS
   SIGNAL eth1g_eth0_ram_mosi        : t_mem_mosi;  -- ETH rx frame and tx frame memory
   SIGNAL eth1g_eth0_ram_miso        : t_mem_miso;
 
-  -- eth1g ch1
+  -- eth1g ch1 (eth_stream only has MM for TSE MAC)
   SIGNAL eth1g_eth1_mm_rst          : STD_LOGIC;
   SIGNAL eth1g_eth1_tse_mosi        : t_mem_mosi;  -- ETH TSE MAC registers
   SIGNAL eth1g_eth1_tse_miso        : t_mem_miso;
-  SIGNAL eth1g_eth1_reg_mosi        : t_mem_mosi;  -- ETH control and status registers
-  SIGNAL eth1g_eth1_reg_miso        : t_mem_miso;
-  SIGNAL eth1g_eth1_reg_interrupt   : STD_LOGIC;   -- Interrupt
-  SIGNAL eth1g_eth1_ram_mosi        : t_mem_mosi;  -- ETH rx frame and tx frame memory
-  SIGNAL eth1g_eth1_ram_miso        : t_mem_miso;
 
   -- EPCS read
   SIGNAL reg_dpmm_data_mosi         : t_mem_mosi;
@@ -648,7 +643,7 @@ BEGIN
     reg_ppsh_mosi            => reg_ppsh_mosi,
     reg_ppsh_miso            => reg_ppsh_miso, 
   
-    -- eth1g ch0
+    -- eth1g ch0 = 1GbE_I
     eth1g_eth0_mm_rst        => eth1g_eth0_mm_rst,
     eth1g_eth0_tse_mosi      => eth1g_eth0_tse_mosi,
     eth1g_eth0_tse_miso      => eth1g_eth0_tse_miso,
@@ -672,15 +667,15 @@ BEGIN
     reg_eth1g_I_strobe_total_count_rx_copi  => reg_eth1g_I_strobe_total_count_rx_copi,
     reg_eth1g_I_strobe_total_count_rx_cipo  => reg_eth1g_I_strobe_total_count_rx_cipo,
 
-    -- eth1g ch1
+    -- eth1g ch1 = 1GbE_II
     eth1g_eth1_mm_rst        => eth1g_eth1_mm_rst,
     eth1g_eth1_tse_mosi      => eth1g_eth1_tse_mosi,
     eth1g_eth1_tse_miso      => eth1g_eth1_tse_miso,
-    eth1g_eth1_reg_mosi      => eth1g_eth1_reg_mosi,
-    eth1g_eth1_reg_miso      => eth1g_eth1_reg_miso,
-    eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
-    eth1g_eth1_ram_mosi      => eth1g_eth1_ram_mosi,
-    eth1g_eth1_ram_miso      => eth1g_eth1_ram_miso,
+    eth1g_eth1_reg_mosi      => OPEN,
+    eth1g_eth1_reg_miso      => c_mem_cipo_rst,
+    eth1g_eth1_reg_interrupt => '0',
+    eth1g_eth1_ram_mosi      => OPEN,
+    eth1g_eth1_ram_miso      => c_mem_cipo_rst,
 
     reg_eth1g_II_bg_ctrl_copi                => reg_eth1g_II_bg_ctrl_copi,
     reg_eth1g_II_bg_ctrl_cipo                => reg_eth1g_II_bg_ctrl_cipo,
@@ -805,10 +800,12 @@ BEGIN
 
 
   gen_udp_stream_1GbE : IF c_use_1GbE_I_UDP = TRUE GENERATE
+    -- Derive MAC/IP/UDP from gn_index
     gn_eth_src_mac_I     <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
     gn_ip_src_addr_I     <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
     gn_udp_src_port_I    <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 0);
 
+    -- Generate UDP Tx and monitor UDP Rx
     u_eth_tester_I : ENTITY eth_lib.eth_tester
     GENERIC MAP (
       g_nof_streams     => c_nof_udp_streams_1GbE_I,
@@ -852,58 +849,21 @@ BEGIN
       reg_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
       reg_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo
     );
+
+    -- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
+    -- to stream UDP data via eth0 = 1GbE-I.
   END GENERATE;
 
 
-  -- Instantiate a second 1GbE to check pinning
+  -- Instantiate a second 1GbE-II to check pinning and to test UDP data via a
+  -- dedicated 1GbE port, instead of multiplexed with M&C
   gen_eth_II: IF c_use_1GbE_II = TRUE GENERATE
-
-    u_eth : ENTITY eth_lib.eth
-    GENERIC MAP (
-      g_technology         => g_technology,
-      g_init_ip_address    => c_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
-      g_cross_clock_domain => TRUE,
-      g_frm_discard_en     => TRUE
-    )
-    PORT MAP (
-      -- Clocks and reset
-      mm_rst            => mm_rst, -- use reset from QSYS
-      mm_clk            => mm_clk,     -- use mm_clk direct
-      --eth_clk           => xo_ethclk,    -- 125 MHz clock
-      eth_clk           => ETH_CLK(1),
-      st_rst            => dp_rst,
-      st_clk            => dp_clk,
-    
-      -- UDP transmit interface
-      udp_tx_snk_in_arr  => (others => c_dp_sosi_rst), 
-      udp_tx_snk_out_arr => open,
-      -- UDP receive interface
-      udp_rx_src_in_arr  => (others => c_dp_siso_rdy),
-      udp_rx_src_out_arr => open,
- 
-      -- Memory Mapped Slaves
-      tse_sla_in        => c_mem_mosi_rst,
-      tse_sla_out       => open,
-      reg_sla_in        => c_mem_mosi_rst,
-      reg_sla_out       => open,
-      reg_sla_interrupt => open,
-      ram_sla_in        => c_mem_mosi_rst,
-      ram_sla_out       => open,
-  
-      -- PHY interface
-      eth_txp           => ETH_SGOUT(1),
-      eth_rxp           => ETH_SGIN(1),
-  
-      -- LED interface
-      tse_led           => open
-    );
-
-    -- TODO: Add control and connect for second 1GbE
-
+    -- Derive eth1 MAC/IP/UDP from eth0
     gn_eth_src_mac_II    <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 1);
     gn_ip_src_addr_II    <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 1);
     gn_udp_src_port_II   <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 1);
 
+    -- Generate UDP Tx and monitor UDP Rx
     u_eth_tester_II : ENTITY eth_lib.eth_tester
     GENERIC MAP (
       g_nof_streams     => c_nof_udp_streams_1GbE_II,
@@ -947,6 +907,48 @@ BEGIN
       reg_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
       reg_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo
     );
+
+    -- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
+    -- stream UDP data via eth1 = 1GbE-II
+    u_eth_stream : ENTITY eth_lib.eth_stream
+    GENERIC MAP (
+      g_technology   => g_technology,
+      g_rx_udp_port  => TO_UINT(c_eth_rx_udp_port),  -- = 0x1771 = 6001
+      g_jumbo_en     => FALSE,
+      g_sim          => g_sim,
+      g_sim_level    => 1   -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+    )
+    PORT MAP (
+      -- Clocks and reset
+      mm_rst             => mm_rst,  -- eth1g_eth1_mm_rst
+      mm_clk             => mm_clk,
+      eth_clk            => ETH_CLK(1),
+      st_rst             => dp_rst,
+      st_clk             => dp_clk,
+
+      -- TSE setup
+      src_mac            => gn_eth_src_mac_II,
+      setup_done         => OPEN,
+
+      -- UDP transmit interface
+      udp_tx_snk_in      => eth1g_II_udp_tx_sosi_arr(0),
+      udp_tx_snk_out     => eth1g_II_udp_tx_siso_arr(0),
+
+      -- UDP receive interface
+      udp_rx_src_in      => c_dp_siso_rdy,
+      udp_rx_src_out     => eth1g_II_udp_rx_sosi_arr(0),
+
+      -- Memory Mapped Slaves
+      tse_ctlr_copi      => eth1g_eth1_tse_mosi,
+      tse_ctlr_cipo      => eth1g_eth1_tse_miso,
+
+      -- PHY interface
+      eth_txp            => ETH_SGOUT(1),
+      eth_rxp            => ETH_SGIN(1),
+
+      -- LED interface
+      tse_led            => OPEN
+    );
   END GENERATE;