Added 100o) Conditional include of IP libraries to avoid Quartus exit due to missing IP signals

tools/hdltool_readme.txt

@@ -695,7 +695,21 @@ m) (FIXED) Issue exit error when a library name occurs double
    
 n) Rename modelsim_compile_ip_files into more precise name eg. modelsim_execute or modelsim_pre_execute
 
-
+o) Conditional include of IP libraries to avoid Quartus exit due to missing IP signals
+   Quartus can exit with error if IP is included in the hdl_lib_uses list of libraries but not actually used in
+   the design, eg due to a sdc file that is then sourced but that cannot find some IP signals.
+   If the error is changed into warning then Quartus continues. Such modification of the sdc file could be automated
+   by using 'sed' to edit the sdc after it was generated by generate_ip.tcl.
+   In some designs we want to be able to temporarily disable the synthesis of an IO component (eg. io_ddr) to reduce
+   synthesis time. In that case the Quartus should not need to source the qip and sdc settings for that IP. It 
+   would be sufficient to only source an io_ddr entity with empty architecture. We already have the revision capability
+   for designs and this could also be applied to IO libraries. Still the question remains how select between using
+   the component declaration only library when it is not used for synthesis and how to include the full library when
+   it is used for synthesis. This could be done if the io_ddr library is only included at the design level, because
+   then the design that uses the io_ddr has hdl_lib_uses = io_ddr in its hdllib.cfg whereas the design that does not
+   use io_ddr should in have hdl_lib_uses = io_ddr_empty, where io_ddr_empty is a revision of io_ddr with only the
+   entity and an emtpy architecture.
+   
 
 101) More ideas