-Changed the bitwidth of the internalcounters. COunters are now based on...

-Changed the bitwidth of the internalcounters. COunters are now based on bitwidth of DDR instead of SOSI. 
-
-Updated comments

libraries/base/reorder/src/vhdl/reorder_sequencer.vhd

@@ -27,7 +27,18 @@
 --              alternated between reads and writes: read periods and write periods.
 --              The number of accesses in a read and wrte period is determined by the 
 --              values of the generic.
---              The generics are interpreted as follows: 
+--              The generics are interpreted as addresses in the sosi clock-domain. If the 
+--              datarate and/or the datawidth of the memory interface is higher than the 
+--              sosi domain than the g_data_w_ratio generic can be used to specify the 
+--              that ratio. An example:
+--
+--                          SOSI DOMAIN    MEMORY DOMAIN (DDR3)
+--              Datawidth      64 bits       256 bits
+--              Clockrate     200 MHz        200 MHz
+--
+--              The g_data_w_ratio should be 4 to facilitate this transition 
+
+--              The meaning of the other generics is explained her: 
 --
 --              - wr_chunksize is the number of samples that are written during a write access.
 --                A write access always consists of 1 access. 
@@ -90,7 +101,8 @@
 --              chunck (0,0) is read from the block 0. The second chunk (0,1) is read
 --              from block 2. The third chunk (1,0) is read from block 4. 
 --
--- Remarks:
+-- Remarks:     If the g_data_w_ratio is used, be sure that the generics wr_chunksize,
+--              rd_chunksize, rd_nof_chunks and gapsize are divisible by g_data_w_ratio.
 
 
 LIBRARY IEEE, common_lib;
@@ -102,8 +114,8 @@ USE work.reorder_pkg.ALL;
 ENTITY reorder_sequencer IS
   GENERIC (
     g_reorder_seq   : t_reorder_seq := c_reorder_seq;
-    g_data_w_ratio  : POSITIVE := 4                 -- (256/64) Ratio between datawidth at the output of the write fifo and the input of the writefifo. 
- );                                                 -- Used to determine the c_address_w. 
+    g_data_w_ratio  : POSITIVE := 1                 -- (256/256) Ratio between datawidth of the memory controller and SOSI domain  
+ );                                                 -- Used to determine the width of counters. 
   PORT (
     -- Clocks and reset
     dp_rst      : IN  STD_LOGIC;  -- reset synchronous with st_clk
@@ -121,11 +133,18 @@ END reorder_sequencer;
 
 
 ARCHITECTURE rtl OF reorder_sequencer IS
+
+  -- Rescale to memory addressing  
+  CONSTANT c_wr_chunksize       : POSITIVE := g_reorder_seq.wr_chunksize/g_data_w_ratio;
+  CONSTANT c_rd_chunksize       : POSITIVE := g_reorder_seq.rd_chunksize/g_data_w_ratio;
+  CONSTANT c_gapsize            : NATURAL  := g_reorder_seq.gapsize/g_data_w_ratio; 
   
-  CONSTANT c_blocksize          : POSITIVE := g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize;  
+  CONSTANT c_blocksize          : POSITIVE := c_wr_chunksize + c_gapsize;  
   CONSTANT c_page_size          : POSITIVE := c_blocksize * g_reorder_seq.nof_blocks;
+  CONSTANT c_mem_size           : POSITIVE := 2*c_page_size;
+  
   CONSTANT c_rd_block_increment : POSITIVE := c_blocksize * g_reorder_seq.rd_interval;
-  CONSTANT c_address_w          : POSITIVE := ceil_log2(2*c_page_size);    
+  CONSTANT c_address_w          : POSITIVE := ceil_log2(c_mem_size);    
   CONSTANT c_address_shift_w    : POSITIVE := ceil_log2(g_data_w_ratio);    
   
   TYPE   state_type is (s_idle, s_write, s_first_write, s_wait_wr, s_read, s_wait_rd);
@@ -138,11 +157,11 @@ ARCHITECTURE rtl OF reorder_sequencer IS
     rd_block_offset  : NATURAL;
     rd_chunks_offset : NATURAL;
     wr_block_offset  : NATURAL;
-    switch_cnt       : NATURAL;   -- Counter that counts the write and read accesses to determine the switch between read and write phase. 
-    page_cnt         : NATURAL;   -- Counter that counts the number of write accesses to determuine the page-swap. 
+    switch_cnt       : NATURAL RANGE 0 TO g_reorder_seq.rd_nof_chunks; -- Counter that counts the write and read accesses to determine the switch between read and write phase. 
+    page_cnt         : NATURAL RANGE 0 TO g_reorder_seq.nof_blocks;    -- Counter that counts the number of write accesses to determine the page-swap. 
     first_write      : STD_LOGIC;
-    start_addr       : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
-    burstsize        : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
+    start_addr       : NATURAL RANGE 0 TO c_mem_size-1;
+    burstsize        : NATURAL RANGE 0 TO sel_a_b(c_wr_chunksize > c_rd_chunksize, c_wr_chunksize, c_rd_chunksize);
     state            : state_type;  -- The state machine. 
   END RECORD;
 
@@ -172,16 +191,16 @@ BEGIN
       WHEN s_first_write =>  
         v.wr_not_rd  := '1'; 
         v.ddr3_en    := '1'; 
-        v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset, c_address_w);
-        v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
+        v.start_addr := r.wr_page_offset + r.wr_block_offset;
+        v.burstsize  := c_wr_chunksize;
         v.state      := s_wait_wr;
         
       WHEN s_write =>  
         IF(done = '1') THEN 
           v.wr_not_rd  := '1'; 
           v.ddr3_en    := '1';
-          v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset, c_address_w);                   
-          v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
+          v.start_addr := r.wr_page_offset + r.wr_block_offset;                   
+          v.burstsize  := c_wr_chunksize;
           v.state      := s_wait_wr; 
         END IF;
 
@@ -197,8 +216,8 @@ BEGIN
           IF( r.first_write = '0') THEN 
             v.ddr3_en := '1'; 
           END IF; 
-          v.start_addr  := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset, c_address_w); 
-          v.burstsize   := TO_UVEC(g_reorder_seq.rd_chunksize, c_address_w);
+          v.start_addr  := r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset; 
+          v.burstsize   := c_rd_chunksize;
           v.switch_cnt  := r.switch_cnt + 1; 
           v.state       := s_wait_rd;
         END IF;
@@ -208,7 +227,7 @@ BEGIN
         v.rd_block_offset := r.rd_block_offset + c_rd_block_increment;
         
         IF(r.rd_block_offset + c_rd_block_increment >= c_page_size) THEN
-          v.rd_chunks_offset := r.rd_chunks_offset + g_reorder_seq.rd_chunksize;   
+          v.rd_chunks_offset := r.rd_chunks_offset + c_rd_chunksize;   
           v.rd_block_offset  := r.rd_block_offset + c_rd_block_increment - c_page_size;     
         END IF;
 
@@ -243,8 +262,8 @@ BEGIN
       v.wr_block_offset  := 0;
       v.rd_block_offset  := 0;
       v.rd_chunks_offset := 0;
-      v.start_addr       := (OTHERS => '0');
-      v.burstsize        := (OTHERS => '0');
+      v.start_addr       := 0;
+      v.burstsize        := 0;
       v.first_write      := '1';
       v.state            := s_idle;
     END IF;
@@ -262,8 +281,8 @@ BEGIN
 
   en_evt      <= r.ddr3_en;
   wr_not_rd   <= r.wr_not_rd;
-  address     <= RESIZE_UVEC(r.start_addr(c_address_w-1 DOWNTO c_address_shift_w), address'LENGTH);
-  burstsize   <= RESIZE_UVEC(r.burstsize(c_address_w-1 DOWNTO c_address_shift_w),  burstsize'LENGTH);
+  address     <= TO_UVEC(r.start_addr, address'LENGTH);
+  burstsize   <= TO_UVEC(r.burstsize,  burstsize'LENGTH);
 
 END rtl;