-SVN copied tb_aartfaac_sdo to RadioHDL.

applications/aartfaac/systems/aartfaac_sdo/hdllib.cfg

+hdl_lib_name = aartfaac_sdo
+hdl_library_clause_name = aartfaac_sdo_lib
+hdl_lib_uses_synth = unb1_board tr_xaui tr_10GbE tr_nonbonded
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity =
+
+quartus_copy_files =
+
+modelsim_copy_files = 
+
+synth_files =
+    src/vhdl/aartfaac_sdo.vhd
+    
+test_bench_files = 
+ 
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    quartus/aartfaac_sdo_pins.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/aartfaac_sdo/sopc_aartfaac_sdo.qip
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    

applications/aartfaac/systems/aartfaac_sdo/tb/vhdl/tb_aartfaac_sdo.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Lets two aartfaac_bn_sdo back nodes send their subband UDP packet stream
+--   to FN aartfaac_fn_sdo which transmits it via its 10GbE interface.
+-- Description:
+-- . The two back nodes use a stream player for faster simulation.
+-- . This test bench is only for verification of the front node design. The
+--   back node design aartfaac_bn_sdo is verified in its own test bench.
+-- . Run this test bench and target FN0 with $AARTFAAC/Software/python/apps/
+--   aartfaac_fn_sdo/yc_aartfaac_fn_sdo_frame_buffer.py to observe the header
+--   fields and incrementing BSN.
+
+LIBRARY IEEE, common_lib, unb_common_lib, mm_lib, aartfaac_bn_sdo_lib, aartfaac_fn_sdo_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE unb_common_lib.unb_common_pkg.ALL;
+USE unb_common_lib.tb_unb_common_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+
+ENTITY tb_aartfaac_sdo IS
+END tb_aartfaac_sdo;
+
+ARCHITECTURE tb OF tb_aartfaac_sdo IS
+
+  CONSTANT c_nof_bn     : NATURAL := 2;
+  CONSTANT c_sim        : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_index  : NATURAL := 0; -- Python can target this test bench @ UniBoard 0, BN 0 and 1.
+  CONSTANT c_bn_id_arr  : t_unb_id_arr(c_nof_bn-1 DOWNTO 0) := ( (TO_UVEC(c_unb_index, c_unb_nof_uniboard_w ) & TO_UVEC(5, c_unb_nof_chip_w)), 
+                                                                 (TO_UVEC(c_unb_index, c_unb_nof_uniboard_w ) & TO_UVEC(4, c_unb_nof_chip_w)) );
+
+   CONSTANT c_fn_id     : STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0) := (TO_UVEC(c_unb_index, c_unb_nof_uniboard_w ) & TO_UVEC(0, c_unb_nof_chip_w));
+
+  ----------------------------------------------------------------------------
+  -- Clocks and resets
+  ----------------------------------------------------------------------------   
+  CONSTANT c_mm_clk_period  : TIME := 100 ps;
+  CONSTANT c_dp_pps_period  : NATURAL := 8;
+  CONSTANT c_tr_clk_period  : TIME := 6.4 ns;
+  CONSTANT c_eth_clk_period : TIME := 40 ns;
+  CONSTANT c_dp_clk_period  : TIME := 5 ns;
+
+  SIGNAL dp_pps             : STD_LOGIC;
+  SIGNAL dp_clk             : STD_LOGIC := '1';
+  SIGNAL dp_rst             : STD_LOGIC := '0';
+
+  SIGNAL tr_clk             : STD_LOGIC := '1';
+
+  SIGNAL eth_clk            : STD_LOGIC := '0';
+
+  SIGNAL bn_mesh_tx_3arr    : t_unb_mesh_sl_3arr;
+  SIGNAL bn_mesh_rx_3arr    : t_unb_mesh_sl_3arr;
+
+  SIGNAL fn_mesh_tx_3arr    : t_unb_mesh_sl_3arr;
+  SIGNAL fn_mesh_rx_3arr    : t_unb_mesh_sl_3arr;
+
+  SIGNAL back_tx_3arr       : t_unb_mesh_sl_3arr;
+  SIGNAL back_rx_3arr       : t_unb_mesh_sl_3arr;
+
+  SIGNAL WDI                : STD_LOGIC;
+  SIGNAL VERSION            : STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0) := "00"; 
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- Clocks
+  ----------------------------------------------------------------------------
+  dp_clk  <= NOT  dp_clk AFTER c_dp_clk_period/2;
+  tr_clk  <= NOT  tr_clk AFTER c_tr_clk_period/2;
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_rst, dp_clk, dp_pps);
+
+  ----------------------------------------------------------------------------
+  -- DUTs
+  ----------------------------------------------------------------------------
+    gen_bn: FOR BN IN 0 TO c_nof_bn-1 GENERATE  
+      ----------------------------------------------------------------------------
+      -- aartfaac_bn_sdo
+      ----------------------------------------------------------------------------
+      u_aartfaac_bn_sdo : ENTITY aartfaac_bn_sdo_lib.aartfaac_bn_sdo
+        GENERIC MAP (
+          g_sim         => c_sim,
+          g_sim_unb_nr  => c_unb_index,
+          g_sim_node_nr => 4+BN,
+          g_design_name => "aartfaac_bn_sdo_lpbk", --Each BN sources its own RSP data
+          g_sim_play_udp_sdo_stream => TRUE -- Greatly reduces sim time.
+        )
+        PORT MAP (
+          -- GENERAL
+          PPS         => dp_pps,
+          WDI         => WDI,
+    
+          -- Others
+          VERSION     => VERSION,
+          ID          => c_bn_id_arr(BN),
+    
+          -- 1GbE Control Interface
+          ETH_clk     => eth_clk,
+          ETH_SGIN    => '0',
+          ETH_SGOUT   => OPEN,
+
+          SA_CLK      => tr_clk,
+          SB_CLK      => tr_clk,
+
+          FN_BN_0_TX  => bn_mesh_tx_3arr(BN)(0),
+          FN_BN_0_RX  => bn_mesh_rx_3arr(BN)(0),
+          FN_BN_1_TX  => bn_mesh_tx_3arr(BN)(1),
+          FN_BN_1_RX  => bn_mesh_rx_3arr(BN)(1),
+          FN_BN_2_TX  => bn_mesh_tx_3arr(BN)(2),
+          FN_BN_2_RX  => bn_mesh_rx_3arr(BN)(2),
+          FN_BN_3_TX  => bn_mesh_tx_3arr(BN)(3),
+          FN_BN_3_RX  => bn_mesh_rx_3arr(BN)(3),
+                      
+          BN_BI_0_TX  => back_tx_3arr(BN)(0),
+          BN_BI_0_RX  => back_rx_3arr(BN)(0),
+          BN_BI_1_TX  => back_tx_3arr(BN)(1),
+          BN_BI_1_RX  => back_rx_3arr(BN)(1),
+          BN_BI_2_TX  => back_tx_3arr(BN)(2),
+          BN_BI_2_RX  => back_rx_3arr(BN)(2),
+          BN_BI_3_TX  => back_tx_3arr(BN)(3),
+          BN_BI_3_RX  => back_rx_3arr(BN)(3)
+        );
+      END GENERATE;
+
+    ----------------------------------------------------------------------------
+    -- Mesh model
+    ----------------------------------------------------------------------------
+    u_mesh_model_sl : ENTITY unb_common_lib.unb_mesh_model_sl
+    GENERIC MAP(
+      g_reorder      => TRUE
+    )
+    PORT MAP (
+      -- FN to BN
+      fn_tx_sl_3arr  => fn_mesh_tx_3arr,
+      bn_rx_sl_3arr  => bn_mesh_rx_3arr,
+      
+      -- BN to FN
+      bn_tx_sl_3arr  => bn_mesh_tx_3arr,
+      fn_rx_sl_3arr  => fn_mesh_rx_3arr
+    );
+
+    ----------------------------------------------------------------------------
+    -- aartfaac_fn_sdo
+    ----------------------------------------------------------------------------
+    u_aartfaac_fn_sdo : ENTITY aartfaac_fn_sdo_lib.aartfaac_fn_sdo
+      GENERIC MAP (
+        g_sim         => c_sim,
+        g_sim_unb_nr  => c_unb_index,
+        g_sim_node_nr => 0
+      )
+      PORT MAP (
+        -- GENERAL
+        PPS         => dp_pps,
+        WDI         => WDI,
+  
+        -- Others
+        VERSION     => VERSION,
+        ID          => c_fn_id,
+  
+        -- 1GbE Control Interface
+        ETH_clk     => eth_clk,
+        ETH_SGIN    => '0',
+        ETH_SGOUT   => OPEN,
+
+        SA_CLK      => tr_clk,
+        SB_CLK      => tr_clk,
+
+        FN_BN_0_TX  => fn_mesh_tx_3arr(0)(0),
+        FN_BN_0_RX  => fn_mesh_rx_3arr(0)(0),
+        FN_BN_1_TX  => fn_mesh_tx_3arr(0)(1),
+        FN_BN_1_RX  => fn_mesh_rx_3arr(0)(1),
+        FN_BN_2_TX  => fn_mesh_tx_3arr(0)(2),
+        FN_BN_2_RX  => fn_mesh_rx_3arr(0)(2),
+        FN_BN_3_TX  => fn_mesh_tx_3arr(0)(3),
+        FN_BN_3_RX  => fn_mesh_rx_3arr(0)(3),
+
+        SI_FN_0_TX  => OPEN,
+        SI_FN_0_RX  => (OTHERS=>'0'),
+
+        SI_FN_1_RX  => (OTHERS=>'0'),
+        SI_FN_2_RX  => (OTHERS=>'0'),
+        SI_FN_3_RX  => (OTHERS=>'0')
+      );
+
+  ----------------------------------------------------------------------------
+  -- BN xcvr interconnects / xcvr loopback
+  -- . Each BN sources its own RSP data
+  ----------------------------------------------------------------------------
+  gen_eth_loopback: FOR i IN 0 TO c_nof_bn-1 GENERATE
+    back_rx_3arr(i) <= back_tx_3arr(i);
+  END GENERATE;
+
+END tb;