Simulated somewhat longer when g_dclk_drift /= 0.

libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd

@@ -58,9 +58,9 @@ USE common_lib.tb_common_pkg.ALL;
 
 ENTITY tb_lvdsh_dd_phs4 IS
   GENERIC (
-     g_dclk_drift         : TIME := 0 ps;      -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
+     g_dclk_drift         : TIME := -2 ps;      -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
                                                -- use factor 2 value because of integer divide by 2 for rising and falling edge per sclk clock period.
-     g_dclk_offon         : BOOLEAN := TRUE;   -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced, use FALSE when g_dclk_drift/=0 ps
+     g_dclk_offon         : BOOLEAN := FALSE;   -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced, use FALSE when g_dclk_drift/=0 ps
      g_dp_phs_clk_period  : NATURAL := 32;     -- number of dp_clk periods per dp_phs_clk period
      g_nof_dp_phs_clk     : NATURAL := 4;      -- nof dp_phs_clk that can be used to detect the lock, use 1 or 4 to ease interpretation of results when g_dclk_drift/=0 ps
      g_dp_phs_clk_en_mask : NATURAL := 16#FF#; -- bit mask to individually enable or disable a dp_phs_clk in range [g_nof_dp_phs_clk-1:0]
@@ -76,7 +76,7 @@ ARCHITECTURE tb OF tb_lvdsh_dd_phs4 IS
   CONSTANT c_wb_factor          : NATURAL := c_dd_factor*c_rx_factor;
   
   CONSTANT c_sim                : BOOLEAN := TRUE;
-  CONSTANT c_tb_duration        : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 1000, 10);   -- nof tb intervals for tb duration
+  CONSTANT c_tb_duration        : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 3000, 10);   -- nof tb intervals for tb duration
   CONSTANT c_tb_init            : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE,   10, 10);   -- nof tb intervals for tb init before verify_en
   
   CONSTANT c_clk_factor         : NATURAL := 100;  -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps