Added new ddr versions

boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd

@@ -75,8 +75,9 @@ ARCHITECTURE tb OF tb_unb1_test IS
   CONSTANT c_sa_clk_period   : TIME := 6.4 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
-  CONSTANT c_use_ddr         : BOOLEAN := g_design_name="unb1_test_ddr" OR g_design_name="unb1_test_all";
-  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+  CONSTANT c_use_ddr_MB_I    : BOOLEAN := g_design_name="unb1_test_ddr_MB_I" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
+  CONSTANT c_use_ddr_MB_II   : BOOLEAN := g_design_name="unb1_test_ddr_MB_II" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
+  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
 
   -- DUT
   SIGNAL clk                 : STD_LOGIC := '0';
@@ -107,10 +108,15 @@ ARCHITECTURE tb OF tb_unb1_test IS
   SIGNAL si_fn_lpbk_2        : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
   SIGNAL si_fn_lpbk_3        : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
 
-  -- Signals to interface with the DDR3 memory model.
-  SIGNAL phy_in              : t_tech_ddr3_phy_in;
-  SIGNAL phy_io              : t_tech_ddr3_phy_io;
-  SIGNAL phy_ou              : t_tech_ddr3_phy_ou;
+  -- Signals to interface with the MB_I DDR3 memory model.
+  SIGNAL phy_MB_I_in         : t_tech_ddr3_phy_in;
+  SIGNAL phy_MB_I_io         : t_tech_ddr3_phy_io;
+  SIGNAL phy_MB_I_ou         : t_tech_ddr3_phy_ou;
+
+  -- Signals to interface with the MB_II DDR3 memory model.
+  SIGNAL phy_MB_II_in        : t_tech_ddr3_phy_in;
+  SIGNAL phy_MB_II_io        : t_tech_ddr3_phy_io;
+  SIGNAL phy_MB_II_ou        : t_tech_ddr3_phy_ou;
 
   -- Model I2C sensor slaves as on the UniBoard
   CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
@@ -202,23 +208,42 @@ BEGIN
       BN_BI_3_TX  => OPEN,
       BN_BI_3_RX  => (OTHERS=>'0'),
 
-      MB_I_IN     => phy_in,
-      MB_I_IO     => phy_io,
-      MB_I_OU     => phy_ou
+      MB_I_IN     => phy_MB_I_in,
+      MB_I_IO     => phy_MB_I_io,
+      MB_I_OU     => phy_MB_I_ou,
+
+      MB_II_IN    => phy_MB_II_in,
+      MB_II_IO    => phy_MB_II_io,
+      MB_II_OU    => phy_MB_II_ou
     );
 
   ------------------------------------------------------------------------------
-  -- DDR3 memory model
+  -- MB_I DDR3 memory model
+  ------------------------------------------------------------------------------
+  gen_tech_ddr_memory_model_MB_I : IF c_use_ddr_MB_I = TRUE GENERATE
+    u_tech_ddr_memory_model_MB_I : ENTITY tech_ddr_lib.tech_ddr_memory_model
+    GENERIC MAP (
+      g_tech_ddr => c_ddr
+    )
+    PORT MAP (
+      mem3_in => phy_MB_I_ou,
+      mem3_io => phy_MB_I_io,
+      mem3_ou => phy_MB_I_in
+    );
+  END GENERATE;
+
+  ------------------------------------------------------------------------------
+  -- MB_II DDR3 memory model
   ------------------------------------------------------------------------------
-  gen_tech_ddr_memory_model : IF c_use_ddr = TRUE GENERATE
-    u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+  gen_tech_ddr_memory_model_MB_II : IF c_use_ddr_MB_II = TRUE GENERATE
+    u_tech_ddr_memory_model_MB_II : ENTITY tech_ddr_lib.tech_ddr_memory_model
     GENERIC MAP (
       g_tech_ddr => c_ddr
     )
     PORT MAP (
-      mem3_in => phy_ou,
-      mem3_io => phy_io,
-      mem3_ou => phy_in
+      mem3_in => phy_MB_II_ou,
+      mem3_io => phy_MB_II_io,
+      mem3_ou => phy_MB_II_in
     );
   END GENERATE;