initial

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -85,11 +85,6 @@ ARCHITECTURE str OF ddrctrl IS
   CONSTANT  c_io_ddr_data_w   : NATURAL                                     := func_tech_ddr_ctlr_data_w( g_tech_ddr );
   CONSTANT  c_wr_fifo_depth   : NATURAL                                     := 256;                                           -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
   CONSTANT  c_rd_fifo_depth   : NATURAL                                     := 256;                                           -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
-  CONSTANT  c_burstsize       : NATURAL                                     := 64;                                            -- max burstsize for max troughput
-  CONSTANT  c_bitshift_adr    : NATURAL                                     := ceil_log2(c_burstsize);
-  CONSTANT  c_adr_w           : NATURAL                                     := func_tech_ddr_ctlr_address_w( g_tech_ddr );    -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
-  CONSTANT  c_max_adr         : NATURAL                                     := 2**(c_adr_w)-1;                                -- the maximal address that is possible within the vector length of the address
-  CONSTANT  c_zeros           : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
 
   -- signals for connecting the components
   SIGNAL    adr          : NATURAL                                          := 0;
@@ -102,23 +97,6 @@ ARCHITECTURE str OF ddrctrl IS
 
 BEGIN
 
-  p_burst : PROCESS(adr)
-  BEGIN
-    IF TO_UVEC(adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
-      dvr_mosi.burstbegin <= '1';
-      IF adr = 0 THEN
-        dvr_mosi.address    <= TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
-      ELSE
-        dvr_mosi.address    <= TO_UVEC(adr-c_burstsize, dvr_mosi.address'length);
-      END IF;
-    ELSE
-      dvr_mosi.burstbegin <= '0';
-    END IF;
-  END PROCESS;
-
-  dvr_mosi.burstsize  <= TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
-  dvr_mosi.wr         <= wr_not_rd;
-  dvr_mosi.rd         <= NOT wr_not_rd;
 
   -- input to io_ddr
   u_ddrctrl_input : ENTITY work.ddrctrl_input

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd

@@ -71,6 +71,7 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
 
   CONSTANT c_t_reg_init     : t_reg         := (RESET, 0, (OTHERS => '0'), 0, 0, 0, c_dp_sosi_init);
 
+
   -- signals for readability
   SIGNAL d_reg              : t_reg         := c_t_reg_init;
   SIGNAL q_reg              : t_reg         := c_t_reg_init;