Merge branch 'L2SDP-415' into 'master'

Added missing REG_STAT_ENABLE_XST and REG_STAT_ENABLE_XST. Removed...

Closes L2SDP-415

See merge request desp/hdl!126

applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml

@@ -101,6 +101,8 @@ peripherals:
       - PIO_JESD_CTRL
       
   - peripheral_name: tech_jesd204b/jesd204b_arria10
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
       - JESD204B
   

libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml

@@ -12,6 +12,7 @@ peripherals:
       # MM port for node_adc_input_and_timing.vhd
       - mm_port_name: PIO_JESD_CTRL
         mm_port_type: REG
+        mm_port_span: 2 * MM_BUS_SIZE
         mm_port_description: ""
         fields:
           - - field_name: reset
@@ -30,11 +31,16 @@ peripherals:
   - peripheral_name: jesd204b_arria10    # pi_jesd204b_unb2.py
     peripheral_description: |
       "M&C of Intel Arria10 JESD204B ADC interface IP, see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf"
+    parameters:
+      # Parameters of tech_jesd204b.vhd
+      - { name: g_nof_streams, value: 1 }
     mm_ports:
       # MM port for tech_jesd204b.vhd
       - mm_port_name: REG_JESD204B
         mm_port_type: REG
+        mm_port_span: 256 * MM_BUS_SIZE   # c_jesd204b_mm_addr_w = 8 bit, see ip_arria10_e1sg_jesd204b.vhd
         mm_port_description: ""
+        number_of_mm_ports: g_nof_streams
         fields:
           - - {field_name: rx_dll_ctrl,             mm_width: 17, bit_offset:  0, access_mode: RW, address_offset: 0x50}
           - - {field_name: rx_syncn_sysref_ctrl,    mm_width: 25, bit_offset:  0, access_mode: RW, address_offset: 0x54}