Time tx_ready and rx_ready after tr_rst release, similar as in sim_10gbase_r.

libraries/technology/xaui/sim_xaui.vhd

@@ -113,7 +113,7 @@ BEGIN
     )
     PORT MAP(
       clk     => tx_clk_arr(i),
-      in_rst  => '0',
+      in_rst  => tr_rst,
       out_rst => txc_tx_ready_arr(i)
     );
     
@@ -125,7 +125,7 @@ BEGIN
     )
     PORT MAP(
       clk     => rx_clk_arr_in(i),
-      in_rst  => '0',
+      in_rst  => tr_rst,
       out_rst => rxc_rx_ready_arr(i)
     );