processed review comments

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -185,7 +185,7 @@ BEGIN
   );
 
   -- Transfer eop counter across clock domains for dual clock
-  gen_dp_fifo_dc : IF g_use_dual_clock=TRUE GENERATE  
+  gen_rd_eop_cnt_dc : IF g_use_dual_clock=TRUE GENERATE  
     reg_wr_eop_cnt <= TO_UVEC(wr_eop_cnt, c_word_w);
     u_common_reg_cross_domain : ENTITY common_lib.common_reg_cross_domain
     PORT MAP (
@@ -202,7 +202,7 @@ BEGIN
   END GENERATE;
     
   -- No need to transfer eop counter across clock domains for single clock
-  gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+  gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE
     wr_fifo_usedw  <= rd_fifo_usedw;
     rd_eop_new     <= '1';
   END GENERATE;