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Commit d22edf11 authored by Priest's avatar Priest
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Newly generated mmm

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applications/compaan/designs/compaan_io_test_fn/src/vhdl/mmm_compaan_io_test_fn.vhd
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View file @ d22edf11
......@@ -51,6 +51,8 @@
-- reg_epcs_miso => reg_epcs_miso,
-- reg_remu_mosi => reg_remu_mosi,
-- reg_remu_miso => reg_remu_miso,
-- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
-- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
-- reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
......@@ -97,6 +99,8 @@
-- SIGNAL reg_epcs_miso : t_mem_miso;
-- SIGNAL reg_remu_mosi : t_mem_mosi;
-- SIGNAL reg_remu_miso : t_mem_miso;
-- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
-- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
-- SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
-- SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
-- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
......@@ -173,6 +177,8 @@ ENTITY mmm_compaan_io_test_fn IS
reg_epcs_miso : IN t_mem_miso := c_mem_miso_rst;
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso := c_mem_miso_rst;
reg_bsn_monitor_mosi : OUT t_mem_mosi;
reg_bsn_monitor_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
......@@ -282,8 +288,10 @@ ARCHITECTURE str OF mmm_compaan_io_test_fn IS
eth1g_reg_read_export : out std_logic;
reg_tr_10gbe_read_export : out std_logic;
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic;
reg_bsn_monitor_reset_export : out std_logic;
eth1g_tse_write_export : out std_logic;
reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_bsn_monitor_write_export : out std_logic;
reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0);
reg_mdio_2_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_tr_xaui_waitrequest_export : in std_logic := '0';
......@@ -300,6 +308,7 @@ ARCHITECTURE str OF mmm_compaan_io_test_fn IS
reg_mdio_2_read_export : out std_logic;
reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0);
reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0);
reg_bsn_monitor_read_export : out std_logic;
reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_2_reset_export : out std_logic;
reg_tr_nonbonded_address_export : out std_logic_vector(3 downto 0);
......@@ -326,15 +335,17 @@ ARCHITECTURE str OF mmm_compaan_io_test_fn IS
reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
eth1g_ram_writedata_export : out std_logic_vector(31 downto 0);
reg_compaan_address_export : out std_logic_vector(18 downto 0);
reg_dp_offload_tx_address_export : out std_logic;
reg_mdio_2_writedata_export : out std_logic_vector(31 downto 0);
reg_dp_offload_tx_address_export : out std_logic;
reg_tr_nonbonded_read_export : out std_logic;
out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0);
reg_mdio_1_address_export : out std_logic_vector(2 downto 0);
reg_tr_xaui_read_export : out std_logic;
reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
pio_system_info_reset_export : out std_logic;
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0);
pio_system_info_read_export : out std_logic;
reg_bsn_monitor_address_export : out std_logic_vector(6 downto 0);
reg_mdio_1_reset_export : out std_logic;
reg_wdi_clk_export : out std_logic;
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
......@@ -346,6 +357,7 @@ ARCHITECTURE str OF mmm_compaan_io_test_fn IS
reg_tr_10gbe_clk_export : out std_logic;
reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic;
out_port_from_the_pio_wdi : out std_logic;
reg_bsn_monitor_clk_export : out std_logic;
eth1g_reg_write_export : out std_logic;
reg_mdio_1_write_export : out std_logic;
reg_compaan_reset_export : out std_logic;
......@@ -364,6 +376,7 @@ ARCHITECTURE str OF mmm_compaan_io_test_fn IS
reg_mdio_0_writedata_export : out std_logic_vector(31 downto 0);
eth1g_tse_waitrequest_export : in std_logic := '0';
reg_tr_10gbe_waitrequest_export : in std_logic := '0';
reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_mm_clk_export : out std_logic;
rom_system_info_reset_export : out std_logic;
reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
......@@ -405,6 +418,8 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_epcs_mosi, reg_epcs_miso );
u_mm_file_reg_remu : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_REMU")
PORT MAP(mm_rst, mm_clk, reg_remu_mosi, reg_remu_miso );
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
......@@ -507,6 +522,13 @@ BEGIN
pio_system_info_reset_export => OPEN,
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 DOWNTO 0),
reg_bsn_monitor_clk_export => OPEN,
reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_reset_export => OPEN,
reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_compaan_address_export => reg_compaan_mosi.address(18 DOWNTO 0),
reg_compaan_clk_export => OPEN,
reg_compaan_read_export => reg_compaan_mosi.rd,
......
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