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Commit d1de5f79 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Pin names and locations for six ADC channel unb2b lab setup.

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applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
+ 97
− 1
View file @ d1de5f79
#Placeholder
###############################################################################
#
# Copyright (C) 2018
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
# Constrain the input I/O path
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# Constrain the output I/O path
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
# False path the PPS to DDIO:
#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
set_time_format -unit ns -decimal_places 3
create_clock -period 125Mhz [get_ports {ETH_CLK}]
create_clock -period 200Mhz [get_ports {CLK}]
create_clock -period 100Mhz [get_ports {CLKUSR}]
create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous -group {CLK}
set_clock_groups -asynchronous -group {BCK_REF_CLK}
set_clock_groups -asynchronous -group {CLK_USR}
set_clock_groups -asynchronous -group {CLKUSR}
set_clock_groups -asynchronous -group {SA_CLK}
set_clock_groups -asynchronous -group {SB_CLK}
# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
# IOPLL outputs (which have global names defined in the IP qsys settings)
set_clock_groups -asynchronous -group [get_clocks pll_clk20]
set_clock_groups -asynchronous -group [get_clocks pll_clk50]
set_clock_groups -asynchronous -group [get_clocks pll_clk100]
set_clock_groups -asynchronous -group [get_clocks pll_clk125]
set_clock_groups -asynchronous -group [get_clocks pll_clk200]
set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400]
# FPLL outputs
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
#set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
# false paths added for the jesd test design
set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+ 3
− 4
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......@@ -31,11 +31,10 @@ quartus_copy_files =
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_pre_files =
../../quartus/lofar2_unb2b_adc.sdc
# use lofar2_unb2b_adc.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
../../quartus/lofar2_unb2b_adc.sdc
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_adc_pins.tcl
......
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+ 30
− 9
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......@@ -70,21 +70,42 @@ ENTITY lofar2_unb2b_adc_full IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
JESD204B_SYNC : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
END lofar2_unb2b_adc_full;
ARCHITECTURE str OF lofar2_unb2b_adc_full IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL jesd204b_sync_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
ARCHITECTURE str OF lofar2_unb2b_adc_full IS
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
JESD204B_SERIAL_DATA(6) <= '0';
JESD204B_SERIAL_DATA(7) <= '0';
JESD204B_SERIAL_DATA(8) <= '0';
JESD204B_SERIAL_DATA(9) <= '0';
JESD204B_SERIAL_DATA(10) <= '0';
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
......@@ -126,11 +147,11 @@ BEGIN
QSFP_LED => QSFP_LED,
-- back transceivers
BCK_RX => BCK_RX,
BCK_REF_CLK => BCK_REF_CLK,
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => JESD204B_SYNC
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => jesd204b_sync_arr
);
END str;
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+ 2
− 2
View file @ d1de5f79
......@@ -77,12 +77,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_rx : STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
BEGIN
......
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+ 28
− 8
View file @ d1de5f79
......@@ -70,21 +70,41 @@ ENTITY lofar2_unb2b_adc_one_node IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
JESD204B_SYNC : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
END lofar2_unb2b_adc_one_node;
ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL jesd204b_sync_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
JESD204B_SERIAL_DATA(6) <= '0';
JESD204B_SERIAL_DATA(7) <= '0';
JESD204B_SERIAL_DATA(8) <= '0';
JESD204B_SERIAL_DATA(9) <= '0';
JESD204B_SERIAL_DATA(10) <= '0';
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
......@@ -126,11 +146,11 @@ BEGIN
QSFP_LED => QSFP_LED,
-- back transceivers
BCK_RX => BCK_RX,
BCK_REF_CLK => BCK_REF_CLK,
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => JESD204B_SYNC
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => jesd204b_sync_arr
);
END str;
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+ 2
− 2
View file @ d1de5f79
......@@ -77,12 +77,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_one_node IS
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_rx : STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
BEGIN
......
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+ 16
− 13
View file @ d1de5f79
......@@ -37,6 +37,7 @@ ENTITY lofar2_unb2b_adc IS
g_design_name : STRING := "lofar2_unb2b_adc";
g_design_note : STRING := "UNUSED";
g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 8192;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
......@@ -76,13 +77,14 @@ ENTITY lofar2_unb2b_adc IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0)
);
END lofar2_unb2b_adc;
......@@ -196,10 +198,10 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
-- WG
SIGNAL reg_wg_mosi_arr : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0);
SIGNAL reg_wg_miso_arr : t_mem_miso_arr(c_nof_streams_input-1 DOWNTO 0);
SIGNAL ram_wg_mosi_arr : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0);
SIGNAL ram_wg_miso_arr : t_mem_miso_arr(c_nof_streams_input-1 DOWNTO 0);
SIGNAL reg_wg_mosi_arr : t_mem_mosi_arr(12-1 DOWNTO 0);
SIGNAL reg_wg_miso_arr : t_mem_miso_arr(12-1 DOWNTO 0);
SIGNAL ram_wg_mosi_arr : t_mem_mosi_arr(12-1 DOWNTO 0);
SIGNAL ram_wg_miso_arr : t_mem_miso_arr(12-1 DOWNTO 0);
-- BSN MONITOR
SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi;
......@@ -454,10 +456,11 @@ BEGIN
u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
GENERIC MAP(
g_sim => g_sim,
g_nof_channels => c_nof_streams_jesd204b
g_nof_channels => c_nof_streams_jesd204b,
g_nof_syncs => c_nof_streams_jesd204b/3 -- Three ADCs per RCU share a sync
)
PORT MAP(
jesd204b_refclk => BCK_REF_CLK,
jesd204b_refclk => JESD204B_REFCLK,
jesd204b_sysref => JESD204B_SYSREF,
jesd204b_sync_n_arr => JESD204B_SYNC,
......@@ -473,7 +476,7 @@ BEGIN
-- Serial
serial_tx_arr => open,
serial_rx_arr => BCK_RX(c_nof_streams_jesd204b-1 downto 0)
serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
);
......@@ -495,7 +498,7 @@ BEGIN
g_technology => g_technology,
g_nof_streams => c_nof_streams_db,
g_data_w => 16,
g_buf_nof_data => 8192, --8192,
g_buf_nof_data => g_buf_nof_data,
g_buf_use_sync => TRUE, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
g_use_rx_seq => FALSE
)
......
applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+ 5
− 5
View file @ d1de5f79
......@@ -77,8 +77,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc IS
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
......@@ -93,7 +93,7 @@ BEGIN
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
......@@ -150,8 +150,8 @@ BEGIN
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => bck_ref_clk,
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
......
applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+ 2
− 2
View file @ d1de5f79
......@@ -224,8 +224,8 @@ BEGIN
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => jesd204b_sampclk_fpga,
JESD204B_SERIAL_DATA => bck_rx,
JESD204B_REFCLK => jesd204b_sampclk_fpga,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref_fpga,
......
boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+ 3
− 0
View file @ d1de5f79
......@@ -87,6 +87,9 @@ PACKAGE unb2b_board_pkg IS
CONSTANT c_unb2b_board_tr_qsfp : t_c_unb2b_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
CONSTANT c_unb2b_board_tr_jesd204b : t_c_unb2b_board_tr := (1, 12, 0); -- per node: 1 buses with 12 channels
CONSTANT c_unb2b_board_nof_tr_jesd204b : NATURAL := 6; --Only 6 channels used in unb2b lab tests
CONSTANT c_unb2b_board_start_tr_jesd204b : NATURAL := 42; --First transceiver used in unb2b lab tests
CONSTANT c_unb2b_board_nof_sync_jesd204b : NATURAL := 2; --Only 6 channels used in unb2b lab tests
CONSTANT c_unb2b_board_tr_qsfp_nof_leds : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
......
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