Expected TSE version depends on FPGA / Uniboard1,2 type.

libraries/technology/tse/tb_tech_tse_with_setup.vhd

@@ -154,6 +154,7 @@ BEGIN
   rx_data <= rx_sosi.data(c_word_w-1 DOWNTO 0);
 
   p_mm_setup : PROCESS
+    VARIABLE v_version : NATURAL;
   BEGIN
     mm_init <= '1';
     mm_copi.wr <= '0';
@@ -170,8 +171,14 @@ BEGIN
     proc_common_wait_some_cycles(mm_clk, 10);
 
     -- Verify external MM access to TSE
-    proc_mem_mm_bus_rd(16#000#, mm_clk, mm_cipo, mm_copi);  -- REV --> CUST_VERSION & 0x0901, 0x1304
-    ASSERT UNSIGNED(mm_rddata(c_16-1 DOWNTO 0)) = X"1304" REPORT "Wrong external MM read access result." SEVERITY ERROR;
+    proc_mem_mm_bus_rd(16#000#, mm_clk, mm_cipo, mm_copi);  -- REV --> CUST_VERSION & 0x0901, 0x1200, 0x1304
+    CASE c_tech_select_default IS
+      WHEN c_tech_stratixiv    => v_version := 16#0901#;  -- unb1
+      WHEN c_tech_arria10_e1sg => v_version := 16#1200#;  -- unb2b
+      WHEN c_tech_arria10_e2sg => v_version := 16#1304#;  -- unb2c
+      WHEN OTHERS              => v_version := 0;  -- default
+    END CASE;
+    ASSERT UNSIGNED(mm_rddata(c_16-1 DOWNTO 0)) = v_version REPORT "Wrong external MM read access result." SEVERITY ERROR;
 
     -- Wait for link synchronisation
     proc_common_wait_until_high(mm_clk, tse_led.link);