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Commit d0381579 authored by Gijs Schoonderbeek's avatar Gijs Schoonderbeek
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Removed extra directory (copy of files)

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1 merge request!310Resolve L2SDP-901
Pipeline #44472 passed
Stage: simulation
Stage: synthesis
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boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/JTAG.lpf deleted 100644 → 0
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LOCATE COMP "CTRL_0" SITE "10" ;
LOCATE COMP "CTRL_1" SITE "9" ;
LOCATE COMP "ENABLE_MSP" SITE "8" ;
LOCATE COMP "IDN_0" SITE "99" ;
LOCATE COMP "IDN_1" SITE "98" ;
LOCATE COMP "IDN_2" SITE "97" ;
LOCATE COMP "IDN_3" SITE "96" ;
LOCATE COMP "LPSEL_0" SITE "18" ;
LOCATE COMP "LPSEL_1" SITE "17" ;
LOCATE COMP "LPSEL_2" SITE "16" ;
LOCATE COMP "LPSEL_3" SITE "15" ;
LOCATE COMP "LPSEL_4" SITE "14" ;
LOCATE COMP "MSPTCK_0" SITE "75" ;
LOCATE COMP "MSPTCK_1" SITE "68" ;
LOCATE COMP "MSPTCK_2" SITE "63" ;
LOCATE COMP "MSPTCK_3" SITE "57" ;
LOCATE COMP "MSPTCK_4" SITE "48" ;
LOCATE COMP "MSPTDI_0" SITE "74" ;
LOCATE COMP "MSPTDI_1" SITE "67" ;
LOCATE COMP "MSPTDI_2" SITE "62" ;
LOCATE COMP "MSPTDI_3" SITE "54" ;
LOCATE COMP "MSPTDI_4" SITE "47" ;
LOCATE COMP "MSPTDO_0" SITE "71" ;
LOCATE COMP "MSPTDO_1" SITE "66" ;
LOCATE COMP "MSPTDO_2" SITE "60" ;
LOCATE COMP "MSPTDO_3" SITE "53" ;
LOCATE COMP "MSPTDO_4" SITE "45" ;
LOCATE COMP "MSPTMS_0" SITE "70" ;
LOCATE COMP "MSPTMS_1" SITE "65" ;
LOCATE COMP "MSPTMS_2" SITE "59" ;
LOCATE COMP "MSPTMS_3" SITE "52" ;
LOCATE COMP "MSPTMS_4" SITE "43" ;
LOCATE COMP "MSPTRST_0" SITE "69" ;
LOCATE COMP "MSPTRST_1" SITE "64" ;
LOCATE COMP "MSPTRST_2" SITE "58" ;
LOCATE COMP "MSPTRST_3" SITE "51" ;
LOCATE COMP "MSPTRST_4" SITE "42" ;
LOCATE COMP "TCK" SITE "85" ;
LOCATE COMP "TDI" SITE "84" ;
LOCATE COMP "TDO" SITE "83" ;
LOCATE COMP "TMS" SITE "82" ;
LOCATE COMP "TRST" SITE "78" ;
LOCATE COMP "CTRL_0" SITE "10" ;
LOCATE COMP "CTRL_1" SITE "9" ;
LOCATE COMP "IDN_0" SITE "99" ;
LOCATE COMP "IDN_1" SITE "98" ;
LOCATE COMP "IDN_2" SITE "97" ;
LOCATE COMP "IDN_3" SITE "96" ;
LOCATE COMP "LPSEL_0" SITE "18" ;
LOCATE COMP "LPSEL_1" SITE "17" ;
LOCATE COMP "LPSEL_2" SITE "16" ;
LOCATE COMP "LPSEL_3" SITE "15" ;
LOCATE COMP "LPSEL_4" SITE "14" ;
LOCATE COMP "MSPTCK_0" SITE "75" ;
LOCATE COMP "MSPTCK_1" SITE "68" ;
LOCATE COMP "MSPTCK_2" SITE "63" ;
LOCATE COMP "MSPTCK_3" SITE "57" ;
LOCATE COMP "MSPTCK_4" SITE "48" ;
LOCATE COMP "MSPTDI_0" SITE "74" ;
LOCATE COMP "MSPTDI_1" SITE "67" ;
LOCATE COMP "MSPTDI_2" SITE "62" ;
LOCATE COMP "MSPTDI_3" SITE "54" ;
LOCATE COMP "MSPTDI_4" SITE "47" ;
LOCATE COMP "MSPTDO_0" SITE "71" ;
LOCATE COMP "MSPTDO_1" SITE "66" ;
LOCATE COMP "MSPTDO_2" SITE "60" ;
LOCATE COMP "MSPTDO_3" SITE "53" ;
LOCATE COMP "MSPTDO_4" SITE "45" ;
LOCATE COMP "MSPTMS_0" SITE "70" ;
LOCATE COMP "MSPTMS_1" SITE "65" ;
LOCATE COMP "MSPTMS_2" SITE "59" ;
LOCATE COMP "MSPTMS_3" SITE "52" ;
LOCATE COMP "MSPTMS_4" SITE "43" ;
LOCATE COMP "MSPTRST_0" SITE "69" ;
LOCATE COMP "MSPTRST_1" SITE "64" ;
LOCATE COMP "MSPTRST_2" SITE "58" ;
LOCATE COMP "MSPTRST_3" SITE "51" ;
LOCATE COMP "MSPTRST_4" SITE "42" ;
LOCATE COMP "CTRL_0" SITE "10" ;
LOCATE COMP "CTRL_1" SITE "9" ;
LOCATE COMP "IDN_0" SITE "99" ;
LOCATE COMP "IDN_1" SITE "98" ;
LOCATE COMP "IDN_2" SITE "97" ;
LOCATE COMP "IDN_3" SITE "96" ;
LOCATE COMP "LPSEL_0" SITE "18" ;
LOCATE COMP "LPSEL_1" SITE "17" ;
LOCATE COMP "LPSEL_2" SITE "16" ;
LOCATE COMP "LPSEL_3" SITE "15" ;
LOCATE COMP "LPSEL_4" SITE "14" ;
LOCATE COMP "MSPTCK_0" SITE "75" ;
LOCATE COMP "MSPTCK_1" SITE "68" ;
LOCATE COMP "MSPTCK_2" SITE "63" ;
LOCATE COMP "MSPTCK_3" SITE "57" ;
LOCATE COMP "MSPTCK_4" SITE "48" ;
LOCATE COMP "MSPTDI_0" SITE "74" ;
LOCATE COMP "MSPTDI_1" SITE "67" ;
LOCATE COMP "MSPTDI_2" SITE "62" ;
LOCATE COMP "MSPTDI_3" SITE "54" ;
LOCATE COMP "MSPTDI_4" SITE "47" ;
LOCATE COMP "MSPTDO_0" SITE "71" ;
LOCATE COMP "MSPTDO_1" SITE "66" ;
LOCATE COMP "MSPTDO_2" SITE "60" ;
LOCATE COMP "MSPTDO_3" SITE "53" ;
LOCATE COMP "MSPTDO_4" SITE "45" ;
LOCATE COMP "MSPTMS_0" SITE "70" ;
LOCATE COMP "MSPTMS_1" SITE "65" ;
LOCATE COMP "MSPTMS_2" SITE "59" ;
LOCATE COMP "MSPTMS_3" SITE "52" ;
LOCATE COMP "MSPTMS_4" SITE "43" ;
LOCATE COMP "MSPTRST_0" SITE "69" ;
LOCATE COMP "MSPTRST_1" SITE "64" ;
LOCATE COMP "MSPTRST_2" SITE "58" ;
LOCATE COMP "MSPTRST_3" SITE "51" ;
LOCATE COMP "MSPTRST_4" SITE "42" ;
boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd deleted 100644 → 0
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-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 - 2008 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
-- Lattice Semiconductor grants permission to use this code for use
-- in synthesis for any Lattice programmable logic product. Other
-- use of this code, including the selling or duplication of any
-- portion is strictly prohibited.
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 | J.O. |11/10/08 |Initial Version
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bscan2 is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
generic ( bscan_ports : positive := 2 );
PORT( TDI, TCK, TMS : in std_logic;
TRST : in std_logic;
-- Turn on slow slew in fitter for output signals
TDO : out std_logic;
-- OE control for MSP ports (Active high)
ENABLE_MSP : in std_logic;
MSPTCK : out std_logic_vector(4*bscan_ports-1 downto 0);
MSPTDI : in std_logic_vector(4*bscan_ports-1 downto 0);
MSPTDO : out std_logic_vector(4*bscan_ports-1 downto 0);
MSPTMS : out std_logic_vector(4*bscan_ports-1 downto 0);
MSPTRST : out std_logic_vector(4*bscan_ports-1 downto 0);
-- one set of addresses to check for device
IDN : in std_logic_vector(3 downto 0)
);
end;
architecture behave of bscan2 is
component top_linker is
-- do not use the generic map to prevent the synthesis tool from
-- appending the number of ports to the components name.
port(TDI, TCK, TMS : in std_logic;
TRST : in std_logic;
-- enable logic for TDO pins.
TDO_enable : out std_logic;
TDO : out std_logic;
MSPCLK : out std_logic_vector(4*bscan_ports downto 1);
MSPTDI : in std_logic_vector(4*bscan_ports downto 1);
MSPTDO : out std_logic_vector(4*bscan_ports downto 1);
MSPTMS : out std_logic_vector(4*bscan_ports downto 1);
MSPTRST : out std_logic_vector(4*bscan_ports downto 1);
-- one set of addresses to check for device
IDN : in std_logic_vector(4 downto 1)
);
end component top_linker;
-- synthesis FILE="top_linker.ngo"
-- logic to enable TDO pins
signal ENABLE_TDO : std_logic;
-- signal from tap controler that enables all TDOs.
signal tdoENABLE : std_logic;
-- logic to generate tdo_sp and tdo_hdr
signal LSPTMS : std_logic_vector(4*bscan_ports-1 downto 0);
signal LSPTCK : std_logic_vector(4*bscan_ports-1 downto 0);
signal LSPTDO : std_logic_vector(4*bscan_ports-1 downto 0);
signal LSPTRST : std_logic_vector(4*bscan_ports-1 downto 0);
-- output of Port Mux
signal TDO_int : std_logic;
begin
-- Wire up all of the tri-state controlled lines automatically
tri_state_lines : for lvar1 in 0 to (4*bscan_ports-1) generate
MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
-- enable MSPTDOs for 1149.1
MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
end generate tri_state_lines;
-- MSP Port enable controls
-- enable logic for all TDO pins
ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
TDO <= TDO_int when tdoENABLE = '1' else 'Z';
TopLinkerModule : component top_linker
port map(
TDO => TDO_int,
TMS => TMS,
TCK => TCK,
TRST => TRST,
TDI => TDI,
TDO_enable => tdoENABLE,
MSPTDI => MSPTDI,
MSPTDO => LSPTDO,
MSPTMS => LSPTMS,
MSPCLK => LSPTCK,
MSPTRST => LSPTRST,
IDN => IDN
);
end behave;
--------------------------------- E O F --------------------------------------
boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top - Copy.vhd deleted 100644 → 0
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---------------------------------------------------------------------------------
--
-- Vhdl file created by I/O Designer
-- Fri Feb 28 17:51:25 2014
--
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity jtag_top is
port (
CTRL : in std_logic_vector (1 downto 0);
ENABLE_MSP : in std_logic;
IDN : in std_logic_vector (3 downto 0);
LPSEL : in std_logic_vector (4 downto 0);
MSPTCK : out std_logic_vector (4 downto 0);
MSPTDI : in std_logic_vector (4 downto 0);
MSPTDO : out std_logic_vector (4 downto 0);
MSPTMS : out std_logic_vector (4 downto 0);
MSPTRST : out std_logic_vector (4 downto 0);
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TMS : in std_logic;
TRST : in std_logic
);
end jtag_top;
boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str) - Copy.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ARCHITECTURE str OF jtag_top IS
COMPONENT bscan2 IS
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
GENERIC (
bscan_ports : POSITIVE := 2
);
PORT (
TDI, TCK, TMS : IN STD_LOGIC;
TRST : IN STD_LOGIC;
-- Turn on slow slew in fitter for output signals
TDO : OUT STD_LOGIC;
-- OE control for MSP ports (Active high)
ENABLE_MSP : IN STD_LOGIC;
MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
-- one set of addresses to check for device
IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT bscan2;
-- internal enable signal for tri-stating the scanbridge
CONSTANT jtag_chains : NATURAL := 5;
SIGNAL ENABLE_SB : STD_LOGIC;
SIGNAL TDO_BSCAN : STD_LOGIC;
SIGNAL TDA : STD_LOGIC;
SIGNAL TDB : STD_LOGIC;
SIGNAL TDC : STD_LOGIC;
SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
BEGIN
bscan : COMPONENT bscan2
PORT MAP (
TDI => TDI,
TCK => TCK,
TMS => TMS,
TRST => TRST,
TDO => TDO_BSCAN,
ENABLE_MSP => ENABLE_SB,
MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
IDN => IDN
);
p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
BEGIN
ENABLE_SB <= '0';
MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
IF LPSEL(4) = '0' THEN
ENABLE_SB <= ENABLE_MSP;
MSPTDO <= MSPTDO_BSCAN;
TDO <= TDO_BSCAN;
MSPTCK <= MSPTCK_BSCAN;
MSPTMS <= MSPTMS_BSCAN;
MSPTRST <= MSPTRST_BSCAN;
else
IF LPSEL(0) = '0' THEN
MSPTDO(0) <= TDI;
TDA <= MSPTDI(0);
MSPTCK(0) <= TCK;
MSPTMS(0) <= TMS;
MSPTRST(0) <= TRST;
ELSE
TDA <= TDI;
END IF;
IF LPSEL(1) = '0' THEN
MSPTDO(1) <= TDA;
TDB <= MSPTDI(1);
MSPTCK(1) <= TCK;
MSPTMS(1) <= TMS;
MSPTRST(1) <= TRST;
ELSE
TDB <= TDA;
END IF;
IF LPSEL(2) = '0' THEN
MSPTDO(2) <= TDB;
TDC <= MSPTDI(2);
MSPTCK(2) <= TCK;
MSPTMS(2) <= TMS;
MSPTRST(2) <= TRST;
ELSE
TDC <= TDB;
END IF;
IF LPSEL(3) = '0' THEN
MSPTDO(3) <= TDC;
TDO <= MSPTDI(3);
MSPTCK(3) <= TCK;
MSPTMS(3) <= TMS;
MSPTRST(3) <= TRST;
ELSE
TDO <= TDC;
END IF;
END IF;
-- old
-- CASE LPSEL IS
-- WHEN "00000" =>
-- ENABLE_SB <= '0';
-- MSPTDO(0) <= TDI;
-- MSPTDO(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
-- TDO <= MSPTDI(0);
-- MSPTCK(0) <= TCK;
-- MSPTCK(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
-- MSPTMS(0) <= TMS;
-- MSPTMS(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
-- MSPTRST(0) <= TRST;
-- MSPTRST(jtag_chains-1 DOWNTO 1) <= "ZZZZ";
-- WHEN "00001" =>
-- ENABLE_SB <= '0';
-- MSPTDO(1) <= TDI;
-- MSPTDO(jtag_chains-1 DOWNTO 2) <= "ZZZ";
-- MSPTDO(0) <= 'Z';
-- TDO <= MSPTDI(1);
-- MSPTCK(1) <= TCK;
-- MSPTCK(jtag_chains-1 DOWNTO 2) <= "ZZZ";
-- MSPTMS(1) <= TMS;
-- MSPTMS(jtag_chains-1 DOWNTO 2) <= "ZZZ";
-- MSPTRST(1) <= TRST;
-- MSPTRST(jtag_chains-1 DOWNTO 2) <= "ZZZ";
-- WHEN "00010" =>
-- ENABLE_SB <= '0';
-- MSPTDO(2) <= TDI;
-- MSPTDO(jtag_chains-1 DOWNTO 3) <= "ZZ";
-- MSPTDO(1 DOWNTO 0) <= "ZZ";
-- TDO <= MSPTDI(2);
-- MSPTCK(2) <= TCK;
-- MSPTCK(jtag_chains-1 DOWNTO 3) <= "ZZ";
-- MSPTMS(2) <= TMS;
-- MSPTMS(jtag_chains-1 DOWNTO 3) <= "ZZ";
-- MSPTRST(2) <= TRST;
-- MSPTRST(jtag_chains-1 DOWNTO 3) <= "ZZ";
-- WHEN "00011" =>
-- ENABLE_SB <= '0';
-- MSPTDO(3) <= TDI;
-- MSPTDO(4) <= 'Z';
-- MSPTDO(2 DOWNTO 0) <= "ZZZ";
-- TDO <= MSPTDI(3);
-- MSPTCK(3) <= TCK;
-- MSPTCK(2 DOWNTO 0) <= "ZZZ";
-- MSPTMS(3) <= TMS;
-- MSPTMS(2 DOWNTO 0) <= "ZZZ";
-- MSPTRST(3) <= TRST;
-- MSPTRST(2 DOWNTO 0) <= "ZZZ";
-- WHEN "00100" =>
-- ENABLE_SB <= '0';
-- MSPTDO(4) <= TDI;
-- MSPTDO(3 DOWNTO 0) <= "ZZZZ";
-- TDO <= MSPTDI(4);
-- MSPTCK(4) <= TCK;
-- MSPTCK(3 DOWNTO 0) <= "ZZZZ";
-- MSPTMS(4) <= TMS;
-- MSPTMS(3 DOWNTO 0) <= "ZZZZ";
-- MSPTRST(4) <= TRST;
-- MSPTRST(3 DOWNTO 0) <= "ZZZZ";
-- WHEN "00101" =>
-- ENABLE_SB <= '0';
-- MSPTDO(0) <= TDI;
-- MSPTDO(1) <= MSPTDI(0);
-- MSPTDO(2) <= MSPTDI(1);
-- MSPTDO(3) <= MSPTDI(2);
-- TDO <= MSPTDI(3);
-- MSPTDO(jtag_chains-1 DOWNTO 4) <= "Z";
-- MSPTCK(0) <= TCK;
-- MSPTCK(1) <= TCK;
-- MSPTCK(2) <= TCK;
-- MSPTCK(3) <= TCK;
-- MSPTCK(jtag_chains-1 DOWNTO 4) <= "Z";
-- MSPTMS(0) <= TMS;
-- MSPTMS(1) <= TMS;
-- MSPTMS(2) <= TMS;
-- MSPTMS(3) <= TMS;
-- MSPTMS(jtag_chains-1 DOWNTO 4) <= "Z";
-- MSPTRST(0) <= TRST;
-- MSPTRST(1) <= TRST;
-- MSPTRST(2) <= TRST;
-- MSPTRST(3) <= TRST;
-- MSPTRST(jtag_chains-1 DOWNTO 4) <= "Z";
-- WHEN "00111" =>
-- ENABLE_SB <= 'Z';
-- MSPTDO(4 DOWNTO 0) <= "ZZZZZ";
-- TDO <= 'Z';
-- MSPTCK(4 DOWNTO 0) <= "ZZZZZ";
-- MSPTMS(4 DOWNTO 0) <= "ZZZZZ";
-- MSPTRST(4 DOWNTO 0) <= "ZZZZZ";
-- WHEN OTHERS =>
-- ENABLE_SB <= ENABLE_MSP;
-- MSPTDO <= MSPTDO_BSCAN;
-- TDO <= TDO_BSCAN;
-- MSPTCK <= MSPTCK_BSCAN;
-- MSPTMS <= MSPTMS_BSCAN;
-- MSPTRST <= MSPTRST_BSCAN;
-- END CASE;
END PROCESS;
END str;
boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ARCHITECTURE str OF jtag_top IS
COMPONENT bscan2 IS
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
GENERIC (
bscan_ports : POSITIVE := 2
);
PORT (
TDI, TCK, TMS : IN STD_LOGIC;
TRST : IN STD_LOGIC;
-- Turn on slow slew in fitter for output signals
TDO : OUT STD_LOGIC;
-- OE control for MSP ports (Active high)
ENABLE_MSP : IN STD_LOGIC;
MSPTCK : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTDI : IN STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTDO : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTMS : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
MSPTRST : OUT STD_LOGIC_VECTOR(4*bscan_ports-1 DOWNTO 0);
-- one set of addresses to check for device
IDN : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT bscan2;
-- internal enable signal for tri-stating the scanbridge
CONSTANT jtag_chains : NATURAL := 5;
SIGNAL ENABLE_SB : STD_LOGIC;
SIGNAL TDO_BSCAN : STD_LOGIC;
SIGNAL TDA : STD_LOGIC;
SIGNAL TDB : STD_LOGIC;
SIGNAL TDC : STD_LOGIC;
SIGNAL TDD : STD_LOGIC;
SIGNAL MSPTDO_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTCK_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTMS_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
SIGNAL MSPTRST_BSCAN : STD_LOGIC_VECTOR(jtag_chains-1 DOWNTO 0);
BEGIN
bscan : COMPONENT bscan2
PORT MAP (
TDI => TDI,
TCK => TCK,
TMS => TMS,
TRST => TRST,
TDO => TDO_BSCAN,
ENABLE_MSP => ENABLE_SB,
MSPTCK(jtag_chains-1 DOWNTO 0) => MSPTCK_BSCAN,
MSPTDI(jtag_chains-1 DOWNTO 0) => MSPTDI,
MSPTDO(jtag_chains-1 DOWNTO 0) => MSPTDO_BSCAN,
MSPTMS(jtag_chains-1 DOWNTO 0) => MSPTMS_BSCAN,
MSPTRST(jtag_chains-1 DOWNTO 0) => MSPTRST_BSCAN,
IDN => "0000"
);
p_jtagselect: PROCESS(TDI,MSPTDI(jtag_chains-1 DOWNTO 0),TCK,TMS,TRST)
BEGIN
ENABLE_SB <= '0';
MSPTDO(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTCK(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTMS(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
MSPTRST(jtag_chains-1 DOWNTO 0) <= "ZZZZZ";
IF CTRL(1) = '1' THEN
ENABLE_SB <= '1';
MSPTDO <= MSPTDO_BSCAN;
TDO <= TDO_BSCAN;
MSPTCK <= MSPTCK_BSCAN;
MSPTMS <= MSPTMS_BSCAN;
MSPTRST <= MSPTRST_BSCAN;
ELSE
IF LPSEL(0) = '0' THEN
MSPTDO(0) <= TDI;
TDA <= MSPTDI(0);
MSPTCK(0) <= TCK;
MSPTMS(0) <= TMS;
MSPTRST(0) <= TRST;
ELSE
TDA <= TDI;
END IF;
IF LPSEL(1) = '0' THEN
MSPTDO(1) <= TDA;
TDB <= MSPTDI(1);
MSPTCK(1) <= TCK;
MSPTMS(1) <= TMS;
MSPTRST(1) <= TRST;
ELSE
TDB <= TDA;
END IF;
IF LPSEL(2) = '0' THEN
MSPTDO(2) <= TDB;
TDC <= MSPTDI(2);
MSPTCK(2) <= TCK;
MSPTMS(2) <= TMS;
MSPTRST(2) <= TRST;
ELSE
TDC <= TDB;
END IF;
IF LPSEL(3) = '0' THEN
MSPTDO(3) <= TDC;
TDD <= MSPTDI(3);
MSPTCK(3) <= TCK;
MSPTMS(3) <= TMS;
MSPTRST(3) <= TRST;
ELSE
TDD <= TDC;
END IF;
IF LPSEL(4) = '0' THEN
MSPTDO(4) <= TDD;
TDO <= MSPTDI(4);
MSPTCK(4) <= TCK;
MSPTMS(4) <= TMS;
MSPTRST(4) <= TRST;
ELSE
TDO <= TDD;
END IF;
END IF;
END PROCESS;
END str;
boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd deleted 100644 → 0
+ 0
− 28
View file @ e6728014
---------------------------------------------------------------------------------
--
-- Vhdl file created by I/O Designer
-- Fri Feb 28 17:51:25 2014
--
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity jtag_top is
port (
CTRL : in std_logic_vector (1 downto 0);
ENABLE_MSP : in std_logic;
IDN : in std_logic_vector (3 downto 0);
LPSEL : in std_logic_vector (4 downto 0);
MSPTCK : out std_logic_vector (4 downto 0);
MSPTDI : in std_logic_vector (4 downto 0);
MSPTDO : out std_logic_vector (4 downto 0);
MSPTMS : out std_logic_vector (4 downto 0);
MSPTRST : out std_logic_vector (4 downto 0);
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TMS : in std_logic;
TRST : in std_logic
);
end jtag_top;
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