Use c_crc_sz = 4 for CRC size in octets instead of hardcoded 4.

libraries/technology/tse/sim_tse.vhd

@@ -84,6 +84,8 @@ END sim_tse;
 
 ARCHITECTURE str OF sim_tse IS
 
+  CONSTANT c_crc_sz : NATURAL := 4;  -- CRC word has 4 octets
+
   SIGNAL tr_clk     : STD_LOGIC;
   SIGNAL tr_rst     : STD_LOGIC;
 
@@ -95,7 +97,7 @@ ARCHITECTURE str OF sim_tse IS
   
   TYPE t_reg IS RECORD
     crc_sosi : t_dp_sosi;
-    crc_cnt  : NATURAL RANGE 0 TO 4;
+    crc_cnt  : NATURAL RANGE 0 TO c_crc_sz;
   END RECORD;
   
   SIGNAL crc_siso      : t_dp_siso := c_dp_siso_hold;
@@ -189,7 +191,7 @@ BEGIN
       -- start with tx_fifo_sosi packet
       tx_pkt_sosi <= tx_fifo_sosi;
       -- append CRC = 0 at end of tx_fifo_sosi packet
-      IF r.crc_sosi.valid='1' THEN
+      IF r.crc_sosi.valid = '1' THEN
         tx_pkt_sosi.data <= TO_DP_DATA(0);
       END IF;
       tx_pkt_sosi.valid <= tx_fifo_sosi.valid OR r.crc_sosi.valid;
@@ -203,17 +205,17 @@ BEGIN
       v := r;
       v.crc_sosi.valid := '0';
       v.crc_sosi.eop := '0';
-      IF tx_fifo_sosi.eop='1' THEN
+      IF tx_fifo_sosi.eop = '1' THEN
         crc_siso.ready <= '0';
         v.crc_sosi.valid := '1';
         v.crc_cnt := 1;
       END IF;
-      IF r.crc_cnt>0 THEN
+      IF r.crc_cnt > 0 THEN
         crc_siso.ready <= '0';
         v.crc_sosi.valid := '1';
         v.crc_cnt := r.crc_cnt + 1;
       END IF;
-      IF r.crc_cnt=3 THEN
+      IF r.crc_cnt = c_crc_sz-1 THEN
         v.crc_sosi.eop := '1';
         v.crc_cnt := 0;
       END IF;
@@ -222,7 +224,7 @@ BEGIN
   
     p_crc_reg : PROCESS(tr_rst, tr_clk)
     BEGIN
-      IF tr_rst='1' THEN
+      IF tr_rst = '1' THEN
         r <= (c_dp_sosi_rst, 0);
       ELSIF rising_edge(tr_clk) THEN
         r <= nxt_r;