cleaned up code st_histogram_8_april, extended testbench

libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd

@@ -62,20 +62,15 @@ ARCHITECTURE rtl OF st_histogram_8_april IS
   SIGNAL init_phase           : STD_LOGIC := '1';
   SIGNAL rd_cnt_allowed       : STD_LOGIC := '0';
   SIGNAL rd_cnt_allowed_pp    : STD_LOGIC := '0';
-  SIGNAL nxt_rd_adr_cnt       : NATURAL := 0;
-  SIGNAL rd_adr_cnt           : NATURAL;-- := 0;
   SIGNAL toggle_detect        : STD_LOGIC := '0';
   SIGNAL toggle_detect_pp     : STD_LOGIC;
   SIGNAL toggle_detect_false  : STD_LOGIC := '1';
---  SIGNAL nxt_toggle_adr_cnt : NATURAL := 0;
---  SIGNAL toggle_adr_cnt     : NATURAL;-- := 0;
   SIGNAL nxt_prev_wrdata      : NATURAL;
   SIGNAL prev_wrdata          : NATURAL;
   SIGNAL prev_prev_wrdata     : NATURAL;
   SIGNAL prev_prev_prev_wrdata: NATURAL;
   SIGNAL sync_detect          : STD_LOGIC := '0';
   SIGNAL sync_detect_pp       : STD_LOGIC;
---  SIGNAL adr_w             : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
   SIGNAL same_r_w_address     : STD_LOGIC;
   SIGNAL same_r_w_address_pp  : STD_LOGIC;
   
@@ -101,12 +96,12 @@ BEGIN
   -- . out : bin_reader_mosi (latency: 0)
   -- . out : bin_reader_mosi_pp (latency: 2)
   -- - out : rd_cnt_allowed_pp  (latency: 2)
-  -- . out : dp_pipeline_src_out_pp (latency: 2)
+  -- . out : dp_pipeline_src_out_pp (latency: 2)                                  -- unnecesary
   -----------------------------------------------------------------------------
   bin_reader_mosi.rd                          <= snk_in.valid; -- when 1, count allowed
   bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low); 
   
-  --snk_in pipeline
+  --snk_in pipeline; Enable sync and valid comparisons
   u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
   GENERIC MAP (
     g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
@@ -120,6 +115,7 @@ BEGIN
   
   init_phase <= '0' WHEN dp_pipeline_src_out_p.sync = '1';
   
+  -- Enable sync comparisons
   u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
   GENERIC MAP (
     g_pipeline   => 2  -- 0 for wires, > 0 for registers, 
@@ -136,17 +132,7 @@ BEGIN
   toggle_detect_false <= '0' WHEN dp_pipeline_src_out_pp.sync = '1';
   sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1' OR dp_pipeline_src_out_pp.sync='1') ELSE '0';
   
---  u_dp_sync_detect_3_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 3  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => sync_detect,
---    src_out      => sync_detect_ppp
---  );
-  
+  -- Line up to p_nxt_bin_writer_mosi process  
   u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -157,19 +143,8 @@ BEGIN
     out_dat => sync_detect_pp
   );
   
-  --prev_bin_reader_mosi pipeline
---  u_dp_pipeline_bin_reader_mosi_1_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => bin_reader_mosi,
---    src_out      => prev_bin_reader_mosi
---  );
-
- 
+  -- Enable adress comparisons 1 cycle back  
+  -- Skip unvalid data with trigger bin_reader_mosi.rd to make comparisons between unvalid-data-seperated data possible.
   u_common_pipeline_bin_reader_mosi_1_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
@@ -184,7 +159,8 @@ BEGIN
     out_dat => prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)
   );
   
-  u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline  -- better to pipeline prev_bin_reader_mosi??
+  -- Enable adress comparisons 2 cycles back
+  u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 1,
@@ -197,7 +173,8 @@ BEGIN
     out_dat => bin_reader_mosi_pp.address(c_adr_w-1 DOWNTO 0)
   );
   
-  u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline  -- better to pipeline prev_bin_reader_mosi??
+  -- Enable adress comparisons 3 cycles back
+  u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline
   GENERIC MAP (
     g_representation => "UNSIGNED", --orig. signed
     g_pipeline       => 2,
@@ -211,24 +188,12 @@ BEGIN
   );
   
   
-  --bin_reader_mosi_pp pipeline
---  u_dp_pipeline_bin_reader_mosi_2_cycle : ENTITY dp_lib.dp_pipeline
---  GENERIC MAP (
---    g_pipeline   => 2  -- 0 for wires, > 0 for registers, 
---  )
---  PORT MAP (
---    rst          => dp_rst,
---    clk          => dp_clk,
---    snk_in       => bin_reader_mosi,
---    src_out      => bin_reader_mosi_pp
---  );
-  
---  rd_cnt_allowed <= snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase = '0') ELSE '0'; -- AND snk_in.sync='0'
+  -- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
   rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( (dp_pipeline_src_out_p.sync='1' AND dp_pipeline_src_out_p.valid='1') OR (dp_pipeline_src_out_pp.sync='1' AND dp_pipeline_src_out_p.valid='1') ) )
-                                 ELSE snk_in.valid WHEN (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND snk_in.sync='0')
+                                 OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
                                  ELSE '0';
   
-  --rd_cnt_allowed_pp pipeline
+  -- Line rd_cnt_allowed up to p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -239,8 +204,12 @@ BEGIN
     out_dat => rd_cnt_allowed_pp
   );
   
-  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0') ELSE '0'; --AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0')
+  -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync
+  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0') ) 
+                                 ELSE '0';
 
+  
+  -- Line up to p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -251,8 +220,10 @@ BEGIN
     out_dat => toggle_detect_pp
   );
   
+  -- Detect an (valid) address that has to be read as well as written at the same time
   same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
   
+  -- Line up top p_nxt_bin_writer_mosi process
   u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP(
     g_pipeline       => 2 -- 0 for wires, > 0 for registers, 
@@ -266,7 +237,7 @@ BEGIN
 
   -----------------------------------------------------------------------------
   -- Bin writer : increments current bin value and sets up write request
-  -- . in  : dp_pipeline_src_out_pp (latency: 2)
+  -- . in  : dp_pipeline_src_out_pp (latency: 2)                                    -- unnecesary ?
   -- . in  : toggle_detect_pp      (latency: 2)
   -- . in  : same_r_w_address_pp   (latency: 2)
   -- . in  : bin_reader_mosi_pp    (latency: 2)
@@ -275,70 +246,59 @@ BEGIN
   -- . out : bin_writer_mosi  (latency: 3)
   -----------------------------------------------------------------------------
   p_nxt_bin_writer_mosi : PROCESS(common_ram_r_w_0_miso, common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata, 
-                                  bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, rd_adr_cnt, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS
+                                  bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS -- dp_pipeline_src_out_pp necesary??
   BEGIN
     nxt_bin_writer_mosi <= c_mem_mosi_rst;
     dbg_state_string <= "unv";
-    IF common_ram_r_w_0_miso.rdval='1' THEN -- OR rd_cnt_allowed_pp = '1'  -- when not same as last 2 adresses
+    IF common_ram_r_w_0_miso.rdval='1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= INCR_UVEC(common_ram_r_w_0_miso.rddata, 1); -- c_word_w); -- depends on count case -- rd_adr_cnt
-      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address; --TODO: what other input do we need for this? -- becomes bin_reader_mosi.address
---      reset count? if toggle detected copy count to toggle counter
+      nxt_bin_writer_mosi.wrdata  <= INCR_UVEC(common_ram_r_w_0_miso.rddata, 1);
+      nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
       nxt_prev_wrdata             <= TO_UINT(common_ram_r_w_0_miso.rddata) + 1;
---      nxt_rd_adr_cnt              <= 0;                                                   -- really necessary ??
       dbg_state_string <= "val";
---      IF bin_reader_mosi_pp.address = bin_reader_mosi.address THEN             -- Double implemented ?? toggle?
---        nxt_toggle_adr_cnt <= INCR_UVEC(common_ram_r_w_0_miso.rddata, 1);      -- Double implemented ??
-    ELSIF toggle_detect_pp = '1' THEN -- dp_pipeline_src_out_pp: 2
+
+    ELSIF toggle_detect_pp = '1' THEN                                                       -- Mist is sensitivity list !
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w); -- prev_wrdata + rd_adr_cnt + toggle_adr_cnt??? + 1  òf prev_prev_wrdata + 1 ??
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
---      nxt_toggle_adr_cnt          <= 0;
       nxt_prev_wrdata             <= prev_prev_wrdata+1;
       dbg_state_string <= "td ";
       
     ELSIF rd_cnt_allowed_pp = '1' THEN
---      nxt_rd_adr_cnt              <= rd_adr_cnt + 1;                                                                                                   -- << !! is rd_adr_cnt really necessary? prev_wrdata might fulfill the need !!
       nxt_bin_writer_mosi.wr      <= '1';
---      IF sync_detect_ppp = '1' THEN
---        nxt_bin_writer_mosi.wrdata <= TO_UVEC( (rd_adr_cnt + 1), c_mem_data_w); -- snk_in.sync (impossible); dp_pipeline_src_out_p (thus 1st cnt): 2 (cnt+1?); dp_pipeline_src_out_pp (1st or maybe 2nd cnt): cnt+1
---        dbg_state_string <= "rs ";
---      ELSE 
-        nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_wrdata + rd_adr_cnt + 1), c_mem_data_w); -- c_word_w); -- maybe RAM + cnt + 1 ??  -- only prev_wrdata + 1 necessary
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_wrdata + 1), c_mem_data_w);
       nxt_prev_wrdata             <= prev_wrdata + 1;
       dbg_state_string <= "r# ";
---      END IF;
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
       
-    ELSIF sync_detect_pp = '1' THEN -- snk_in.sync at least -- good as it is!
+    ELSIF sync_detect_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
       nxt_bin_writer_mosi.wrdata  <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; dp_pipeline_src_out_p.sync (thus new adress): 1; dp_pipeline_src_out_pp.sync (thus new adress): 1
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
---      nxt_rd_adr_cnt              <= 0;                             -- really necessary ??
       nxt_prev_wrdata             <= 1;
       dbg_state_string  <= "sd ";
       
     ELSIF same_r_w_address_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);       -- Misses in sensitivity list !
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
       nxt_prev_wrdata             <= prev_prev_prev_wrdata + 1;
       dbg_state_string  <= "srw";
     END IF;
   END PROCESS; 
 
-  p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_rd_adr_cnt, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS
+  p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS
   BEGIN
     IF dp_rst = '1' THEN
        bin_writer_mosi <= c_mem_mosi_rst;
     ELSIF RISING_EDGE(dp_clk) THEN
        bin_writer_mosi <= nxt_bin_writer_mosi;
---       rd_adr_cnt      <= nxt_rd_adr_cnt;
---       toggle_adr_cnt  <= nxt_toggle_adr_cnt;
+       IF nxt_bin_writer_mosi.wr = '1' THEN
          prev_wrdata     <= nxt_prev_wrdata;
-       prev_prev_wrdata<= prev_wrdata;
+         prev_prev_wrdata<= prev_wrdata;               -- wrong when unvalid before toggle_detect_pp; may not shift wrdata when unvalid
          prev_prev_prev_wrdata <= prev_prev_wrdata;
        END IF;
+    END IF;
   END PROCESS;
 
 
@@ -351,10 +311,11 @@ BEGIN
   -- . out : bin_arbiter_rd_mosi (latency: 1)
   -- .     : bin_arbiter_wr_mosi (latency: 4)
   -----------------------------------------------------------------------------
-  nxt_bin_arbiter_wr_mosi <= bin_writer_mosi; --TODO - The rd and wr mosi should not have the same address.          v met 2 cycles rd mag, met 3 cycles niet, dus klopt dit wel?, moet hier niet bin_reader_mosi_pp staan? --AND !(A=B)
+  nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
+  -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to
   nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) ) 
-                                                         -- AND sync_detect='0')
-                                                   OR (init_phase = '1') ELSE '0';                                                                                       -- bin_writer_mosi(adress 3cycles ago?) .address when .rd='1' ????
+                                                         -- AND sync_detect='0')                                                                                  -- activate sync !
+                                                   OR (init_phase = '1') ELSE '0';
   nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
 
   p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi) IS

libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd

@@ -46,6 +46,7 @@
 
 LIBRARY IEEE, common_lib, mm_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;           -- needed by TO_UNSIGNED
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
@@ -59,8 +60,8 @@ ENTITY tb_st_histogram IS
     g_nof_bins             : NATURAL := 8; --8 ; 2
     g_nof_data             : NATURAL := 200;
     --g_str                  : STRING  := "freq.density";
-    g_valid_gap            : BOOLEAN := TRUE;
-    g_snk_in_data_sim_type : STRING  := "counter"  -- "counter" or "toggle" or "same rw" or "mix"
+    g_valid_gap            : STRING  := "custom"; -- "false" or "true" or "custom" --BOOLEAN := TRUE
+    g_snk_in_data_sim_type : STRING  := "same rw"  -- "counter" or "toggle" or "same rw" or "mix"
     );
 END tb_st_histogram;
 
@@ -79,6 +80,7 @@ ARCHITECTURE tb OF tb_st_histogram IS
   SIGNAL prev_unvalid           : STD_LOGIC := '0';
   SIGNAL init_phase             : STD_LOGIC := '1';
   SIGNAL toggle_start           : STD_LOGIC := '0';
+  SIGNAL pre_sync               : STD_LOGIC := '0';
   
   
   ----------------------------------------------------------------------------
@@ -87,10 +89,26 @@ ARCHITECTURE tb OF tb_st_histogram IS
   TYPE t_srw_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
   CONSTANT c_srw_arr            : t_srw_arr := (0,0,1,1,0,0,1,2,3, 1, 2, 3, 0, 3, 3, 0, 3);
                                             --  1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
+                                            --0:1.2.    3.4.               05.      06.
+                                            --1:    1.2.    3.    04.
+                                            --2:              1.     02.
+                                            --3:                1.      02.   03.04.   05.
+                                            --srw:      x.  x.     x. x. x.       x. x. u.
   
   SIGNAL srw_index_cnt          : NATURAL   := 0;
   
   
+  ----------------------------------------------------------------------------
+  -- Valid stimuli
+  ----------------------------------------------------------------------------
+  TYPE t_val_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  CONSTANT c_val_arr            : t_val_arr := (1,1,1,1,0,1,1,1,1, 1, 1, 1, 1, 0, 1, 1, 1);
+                                            --  1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
+  
+  SIGNAL val_index_cnt          : NATURAL   := 0;
+  SIGNAL dbg_valid              : NATURAL;
+  
+  
   ----------------------------------------------------------------------------
   -- Clocks and resets
   ----------------------------------------------------------------------------   
@@ -162,7 +180,7 @@ BEGIN
     ELSIF g_snk_in_data_sim_type = "same rw" THEN
       IF dp_rst='1' THEN
         st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
-      ELSIF rising_edge(dp_clk) AND pre_valid='1' THEN -- AND init_phase='0'   didn't work
+      ELSIF rising_edge(dp_clk) AND pre_sync='1' THEN -- AND init_phase='0'   didn't work
         st_histogram_snk_in.data(g_data_w-1 DOWNTO c_adr_low) <= TO_UVEC(c_srw_arr(srw_index_cnt), c_adr_w); --placeholder !
         IF srw_index_cnt = c_srw_arr'LENGTH -1 THEN
           srw_index_cnt <= 0;
@@ -209,7 +227,7 @@ BEGIN
   
   p_stimuli : PROCESS
   BEGIN
-    IF g_valid_gap = FALSE THEN
+    IF g_valid_gap = "false" THEN
     
       -- initializing
       st_histogram_snk_in.sync <= '0';
@@ -233,13 +251,15 @@ BEGIN
       tb_end <= '1';
       WAIT;
       
-    ELSIF g_valid_gap = TRUE THEN
+    ELSIF g_valid_gap = "true" THEN
     
       -- initializing
       st_histogram_snk_in.sync <= '0';
       st_histogram_snk_in.valid <= '0';
       WAIT UNTIL rising_edge(dp_clk);
-      FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      pre_sync <= '1';
+      WAIT UNTIL rising_edge(dp_clk);
       pre_valid <= '1';
       st_histogram_snk_in.valid <= '1';
       -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
@@ -276,6 +296,36 @@ BEGIN
       FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
       tb_end <= '1';
       WAIT;
+      
+    ELSIF g_valid_gap = "custom" THEN
+      
+      -- initializing
+      st_histogram_snk_in.sync <= '0';
+      st_histogram_snk_in.valid <= '0';
+      WAIT UNTIL rising_edge(dp_clk);
+      FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      pre_sync <= '1';
+      WAIT UNTIL rising_edge(dp_clk);
+      pre_valid <= '1';
+ --     st_histogram_snk_in.valid <= '1';
+      -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
+      FOR I IN 0 TO g_nof_sync-2 LOOP
+        toggle_start <= '1';
+        st_histogram_snk_in.sync <= '1';
+        st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED(c_val_arr(0),1)(0) ); -- TO_UVEC(c_val_arr(0), c_adr_w); --placeholder !
+        WAIT UNTIL rising_edge(dp_clk);
+        st_histogram_snk_in.sync <= '0';
+        FOR I IN 1 TO c_val_arr'LENGTH -1 LOOP
+          st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED( c_val_arr(I) ,1)(0) ); -- TO_UVEC(c_val_arr(J), c_adr_w);
+          dbg_valid <= I;
+          WAIT UNTIL rising_edge(dp_clk);
+        END LOOP;
+        proc_common_wait_some_cycles(dp_clk, (g_sync_length - (c_val_arr'LENGTH -2) ));
+      END LOOP;
+      -- ending
+      FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+      tb_end <= '1';
+      WAIT;
     END IF;
   END PROCESS;