Cope with g_data_w > 2*c_dp_stream_dsp_data_w.

libraries/base/dp/src/vhdl/dp_fifo_core.vhd

@@ -89,7 +89,7 @@ ARCHITECTURE str OF dp_fifo_core IS
   CONSTANT c_use_data         : BOOLEAN := TRUE;
   CONSTANT c_ctrl_w           : NATURAL := 2;  -- sop and eop
 
-  CONSTANT c_complex_w        : NATURAL := g_data_w/2;
+  CONSTANT c_complex_w        : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2);  -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
    
   CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin;  -- FIFO almost full level for snk_out.ready
   CONSTANT c_fifo_dat_w       : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
@@ -99,8 +99,9 @@ ARCHITECTURE str OF dp_fifo_core IS
   
   SIGNAL arst          : STD_LOGIC;
     
-  SIGNAL wr_data       : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
-  SIGNAL rd_data       : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+  SIGNAL wr_data_complex : STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
+  SIGNAL wr_data         : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+  SIGNAL rd_data         : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
 
   SIGNAL fifo_wr_dat   : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
   SIGNAL fifo_wr_req   : STD_LOGIC;
@@ -142,7 +143,8 @@ BEGIN
   wr_ctrl    <= snk_in.sop & snk_in.eop;
 
   -- Assign the snk_in data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
-  wr_data <= snk_in.data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE snk_in.im(c_complex_w-1 DOWNTO 0) & snk_in.re(c_complex_w-1 DOWNTO 0);
+  wr_data_complex <= snk_in.im(c_complex_w-1 DOWNTO 0) & snk_in.re(c_complex_w-1 DOWNTO 0);  
+  wr_data         <= snk_in.data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex, g_data_w);
   
   -- fifo wr wires
   fifo_wr_req <= snk_in.valid;
@@ -216,8 +218,8 @@ BEGIN
   
   -- SOSI
   rd_sosi.data(      g_data_w-1 DOWNTO 0) <= rd_data;
-  rd_sosi.re(     c_complex_w-1 DOWNTO 0) <= rd_data(g_data_w/2-1 DOWNTO 0);
-  rd_sosi.im(     c_complex_w-1 DOWNTO 0) <= rd_data(g_data_w-1   DOWNTO g_data_w/2);
+  rd_sosi.re(     c_complex_w-1 DOWNTO 0) <= rd_data(  c_complex_w-1 DOWNTO 0);
+  rd_sosi.im(     c_complex_w-1 DOWNTO 0) <= rd_data(2*c_complex_w-1 DOWNTO c_complex_w);
   rd_sosi.bsn(        g_bsn_w-1 DOWNTO 0) <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 1);
   rd_sosi.empty(    g_empty_w-1 DOWNTO 0) <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 2);
   rd_sosi.channel(g_channel_w-1 DOWNTO 0) <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 3);