g_wait_last_evt:NATURAL:=100-- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
);
);
PORT(
PORT(
rst:INSTD_LOGIC;
rst:INSTD_LOGIC;
...
@@ -168,7 +169,7 @@ BEGIN
...
@@ -168,7 +169,7 @@ BEGIN
last_snk_in<=v_last;
last_snk_in<=v_last;
-- Signal end of stimuli
-- Signal end of stimuli
proc_common_wait_some_cycles(clk,100);-- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
proc_common_wait_some_cycles(clk,g_wait_last_evt);-- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through