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Commit ce7506ea authored by Eric Kooistra's avatar Eric Kooistra
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Added g_wait_last_evt to allow for more latency in DUT.

parent 319bdbcb
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...@@ -62,7 +62,8 @@ ENTITY dp_stream_stimuli IS ...@@ -62,7 +62,8 @@ ENTITY dp_stream_stimuli IS
g_in_dat_w : NATURAL := 32; g_in_dat_w : NATURAL := 32;
g_nof_repeat : NATURAL := 5; g_nof_repeat : NATURAL := 5;
g_pkt_len : NATURAL := 16; g_pkt_len : NATURAL := 16;
g_pkt_gap : NATURAL := 4 g_pkt_gap : NATURAL := 4;
g_wait_last_evt : NATURAL := 100 -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
); );
PORT ( PORT (
rst : IN STD_LOGIC; rst : IN STD_LOGIC;
...@@ -168,7 +169,7 @@ BEGIN ...@@ -168,7 +169,7 @@ BEGIN
last_snk_in <= v_last; last_snk_in <= v_last;
-- Signal end of stimuli -- Signal end of stimuli
proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through proc_common_wait_some_cycles(clk, g_wait_last_evt); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
proc_common_gen_pulse(clk, last_snk_in_evt); proc_common_gen_pulse(clk, last_snk_in_evt);
proc_common_wait_some_cycles(clk, 50); proc_common_wait_some_cycles(clk, 50);
tb_end <= '1'; tb_end <= '1';
......
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