Added regression_test_vhdl key, but no tb.

libraries/io/ddr3/hdllib.cfg

@@ -22,6 +22,9 @@ test_bench_files =
     tb/vhdl/tb_seq_ddr3.vhd
     tb/vhdl/tb_ddr3_transpose.vhd
 
+regression_test_vhdl = 
+    #tb/vhdl/tb_ddr3.vhd   -- tb fails, ddr3 library may be obsolete, better use io_ddr
+
 
 [modelsim_project_file]
 modelsim_copy_files =