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Commit ce6b96ee authored by Eric Kooistra's avatar Eric Kooistra
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Marked more text as done = processed into confluence doc.

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applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
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......@@ -364,46 +364,48 @@ Design options:
that any input in the buffers can still be output at the correct instant. If all buffers are empty then
input realignment is needed.
- The alignment becomes easier if:
- Done: The alignment becomes easier if:
. it is not done on the entire 64 bit BSN, but only on a periodic fraction r of the BSN,
. the periodic BSN has a period that is a power of 2, so r = BSN[R-1:0].
. it is not done on any BSN, but only on a certain periodic BSN marked by an align_sync pulse at r = 0.
. Done: it is not done on the entire 64 bit BSN, but only on a periodic fraction r of the BSN,
. Done: the periodic BSN has a period that is a power of 2, so r = BSN[R-1:0].
. Ignore: it is not done on any BSN, but only on a certain periodic BSN marked by an align_sync pulse at r = 0.
The advantage of using a BSN fraction is that it smaller to handle and that it can be used
Done: The advantage of using a BSN fraction is that it smaller to handle and that it can be used
as index to a block in the input buffer. The fraction r of the BSN must be unique over the maximum input
latency, so r >= g_bsn_latency. The calculation of the BSN fraction r becomes easier, by choosing a fraction
that is a power of 2, so r = 2**ceil_log2(g_bsn_latency), to avoid integer division. The BSN fraction then
follows directly from the R = log2(r) LSbits of the BSN, so r = BSN[R-1:0]. The advantange of detecting the
alignment only at a certain periodic BSN is that the initial block index is then fixed at a certain r,
choose r = 0. it is convenient to mark the periodic BSN fraction at r = 0 by a sync pulse that is called the
align_sync.
The align_sync is only used within the BSN aligner. If alignment fails on an align_sync, due to a lost
packet, then the intial alignment retries on the next align_sync. The minimal period of the align_sync
must be large enough to ensure that the input buffers will only contain corresponding align_sync and no
align_sync from different intervals. Hence the align_sync period must be > BSN latency + buffer size.
Without align_sync the buffer would need to be twice as large to ensure unambigous detection of alignment.
follows directly from the R = log2(r) LSbits of the BSN, so r = BSN[R-1:0].
Ignore: The advantange of detecting the alignment only at a certain periodic BSN is that the initial block
index is then fixed at a certain r, choose r = 0. it is convenient to mark the periodic BSN fraction at
r = 0 by a sync pulse that is called the align_sync.
Ignore: The align_sync is only used within the BSN aligner. If alignment fails on an align_sync, due to a lost
packet, then the intial alignment retries on the next align_sync.
Not true: The minimal period of the align_sync must be large enough to ensure that the input buffers will only contain
corresponding align_sync and no align_sync from different intervals. Hence the align_sync period must be
> BSN latency + buffer size.
Not true: Without align_sync the buffer would need to be twice as large to ensure unambigous detection of alignment.
The align_sync period must be short enough to have a fast initial alignment. The 1 s sync interval could
be used as align_sync, but in LOFAR2.0 the 1 s sync BSN period is not a power of two and differs by 1 per
sync interval, so the sync appears at different block indices. Furthermore a 1 s period is relatively long,
using a dedicated and much shorter align_sync period allows fast initial alignment.
- For the ring the latency depends on the number of hops. Therefore require that initial BSN alignment is achieved
- Ignore: For the ring the latency depends on the number of hops. Therefore require that initial BSN alignment is achieved
with all active input as defined by M&C, to ensure that the total input latency at each node on the ring is
determined by the nominal operation.
==> Design decision:
- Use input buffer size > g_bsn_latency to compensate for the maximum BSN latency difference between inputs
- Use an align_sync period > g_bsn_latency + buffer size to start initial alignment and to ensure,
==> Done: Design decision:
- Done: Use input buffer size > g_bsn_latency to compensate for the maximum BSN latency difference between inputs
- Do not: Use an align_sync period > g_bsn_latency + buffer size to start initial alignment and to ensure,
together with the validation of the BSN at sync, the unambigous detection of input alignment on the same BSN
. Input buffer type
. Done: Input buffer type
The input buffer can be structured as:
- a circular buffer that can be accessed at any address, or
- a FIFO buffer that is used first in first out.
- Done: a circular buffer that can be accessed at any address, or
- Do not: a FIFO buffer that is used first in first out.
Done/ignore:
In a circular buffer each input block will occupy a slot that is identified by the block index r. For each slot
there is a write (Wr) flag that is set when the block is written and cleared when the block is read for output
or discarded. The slots in the circular buffer have the fixed block size, so therefore the sop and eop of the
......@@ -422,7 +424,7 @@ Design options:
3 4 5 6 7 A 1 2 . . . W W . . 3 4 W . 3 4 5 W 3 4 5 6 W W 5 6 7 A W 6 7 0 1 W 7
2 3 4 5 6 7 A 1 . . W . . . 2 W W . 2 3 4 W 2 3 4 5 W 3 4 5 6 W W 5 6 7 0 W 6 7
R R
Do not:
In a FIFO buffer each input block is written at the first free location, so in order of arrival. A lost packet
does not show in the FIFO, so therefore the block index r needs to be passed along with the block through the
FIFO and checked at the output. It is convenient to pass on the sop and eop information with the block through
......@@ -441,43 +443,43 @@ Design options:
2 3 4 5 6 7 A 1 . . . . . . . . . . . . . . . . . . . . . . . . W . . . W . . .
R R
Both the buffers need to pass on the sync information per block, to allow timestamp recovery from Station BSN
Ignore:Both the buffers need to pass on the sync information per block, to allow timestamp recovery from Station BSN
for the BSN aligner output.
The aspects of a circular buffer are:
- can handle out-of-order data, because it uses the BSN fraction as slot index. However on the ring in SDP all
Done: The aspects of a circular buffer are:
- Done: can handle out-of-order data, because it uses the BSN fraction as slot index. However on the ring in SDP all
data will be in order.
- if initial alignment fails it automatically retries on the next align_sync.
- the BSN must be continuous and incrementing, because then the remainder of the BSN / buffer size can
- Ignore: if initial alignment fails it automatically retries on the next align_sync.
- Done: the BSN must be continuous and incrementing, because then the remainder of the BSN / buffer size can
be used as Wr pointer.
- to avoid integer division of the Station BSN the buffer size needs to be a power of 2
- Done: to avoid integer division of the Station BSN the buffer size needs to be a power of 2
The aspects of a FIFO buffer are:
- during initital alignment lost packets on one input will cause other inputs to overflow.
- FIFO overflow can occur due to lost packets on an other input or when the initial alignment started while
Not used: The aspects of a FIFO buffer are:
- Ignore: during initital alignment lost packets on one input will cause other inputs to overflow.
- Ignore: FIFO overflow can occur due to lost packets on an other input or when the initial alignment started while
align_sync from the different inputs are arriving. The align_sync period needs to be large enough to
ensure that at a next attempt all align_sync will be for the corresponding BSN. The overflow requires a
restart of the initial alignment by flushing the FIFOs.
- easy to use a buffer size that is not a power of 2, because the block index is not used as Wr pointer index.
- Ignore: easy to use a buffer size that is not a power of 2, because the block index is not used as Wr pointer index.
Using a buffer size that is not a power of 2 can be significant to save RAM.
- Passing on the BSN fraction r via the FIFO may increase the number RAM, dependent on whether the combination
- Ignore: Passing on the BSN fraction r via the FIFO may increase the number RAM, dependent on whether the combination
of data, sop, eop, sync, align_sync and r just fits in a multiple of the maximum data with of a block RAM
- The BSN index does not have to be incrementing, but is must be unique per BSN latency interval
- Ignore: The BSN index does not have to be incrementing, but is must be unique per BSN latency interval
- Input / output control
. The BSN aligner can operate independently per input / output. The only interaction between inputs is needed
- Ignore: Input / output control
. Ignore: The BSN aligner can operate independently per input / output. The only interaction between inputs is needed
to detect that all inputs have a pending align_sync. The local block reference for block output can be
shared for all outputs, or replicated per output.
. The 1 s sync does not have to be checked at the outputs, because if the sync is present on one output, then
. Ignore: The 1 s sync does not have to be checked at the outputs, because if the sync is present on one output, then
it will be present on all outputs.
- Flushing:
. Circular buffer:
. Done: Circular buffer:
- Clearing a Wr flag or all Wr flags is much faster than flush reading a FIFO.
. FIFO buffer:
. Ignore: FIFO buffer:
- flush per packet or flush until empty?
- flush per input per input or flush all inputs?
- flush by reading, or by reset or by moving a Rd pointer
......@@ -495,22 +497,22 @@ Design options:
corresponded to the lost packet will need to be discarded anyway, because there is no time to output them still.
- also useful to know BSNs at FIFO inputs? --> No, because FIFO packet count can be used to detect pending FIFO overflow.
. Keep input buffers outside or inside BSN aligner component.
- for inputs with more latency the buffer can be smaller, this is easier to control with external buffers,
. Ignore: Keep input buffers outside or inside BSN aligner component.
- Ignore: for inputs with more latency the buffer can be smaller, this is easier to control with external buffers,
each input may have different g_bsn_latency, so then each input also has different align timeout, align_sync
interval and input FIFO size.
- if the BSN aligner relies on FIFO input information, then it is better to have the FIFOs inside.
- Ignore: if the BSN aligner relies on FIFO input information, then it is better to have the FIFOs inside.
- Fast integer division
- Ignore: Fast integer division
. Modulo 2**n - 1 can be calculated efficiently for binary numbers, by adding the n-bit digit parts. Similar as
mpdulo 3 (= (10-1)/3) can be calculated by adding the decimal digits.
. Modulo n for constant n can be calculated efficiently suing multiplication by 1/n. The 1/n fraction must be
. Modulo n for constant n can be calculated efficiently using multiplication by 1/n. The 1/n fraction must be
represented with sufficient accuracy to determine the remainder. This implies using a 50 bit multiplier,
because the Station BSN is 50 bit.
. Circular buffers on CEP
. Done: Circular buffers on CEP
On CEP the beamlet data is written into a circular buffer based on the time stamp. A flag indicates whether data in the
circular buffer is valid. The size of the circular buffer is in the order of hundreds of ms to cover the distance latency
of the international stations. An array of tupples lists the lenght of continuous blocks in the circular buffer, and
......@@ -519,7 +521,7 @@ Design options:
also flags the initial channel data that is disturbed after a gap.
. State machine for circular buffer
. Ignore: State machine for circular buffer
all:
Receive and monitor input
Derive align_sync from input BSN
......@@ -544,7 +546,7 @@ Design options:
output one block, use filler data for lost blocks, clear Wr flag of slot and increment Rd pointer --> s_sop
. State machine for FIFO buffer
. Do not: State machine for FIFO buffer
all:
Receive and monitor input
Derive align_sync from input BSN
......@@ -567,7 +569,7 @@ Design options:
else
output one block, use filler data for lost blocks --> s_sop
==> Design decision:
==> Done: Design decision:
The circular buffer and FIFO are similar. The slight preference is to use a circular buffer, because it
handles overflow automatically and if the maximum input BSN latency is close to a power of 2, then the
RAM usage of the circular buffer is near optimal, because it does not need to pass on the sop, eop and
......@@ -575,7 +577,7 @@ Design options:
Obsolete investigations:
Ignore: Obsolete investigations:
. APERTIF BSN max/min scheme of dp_bsn_align.vhd core:
- State machine
......
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