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Commit cd4121de authored by Reinier van der Walle's avatar Reinier van der Walle
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added missing scynchronization

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1 merge request!178added missing scynchronization
Pipeline #22273 passed
Stage: simulation
Stage: synthesis
Stage: hardware
Pipeline: sdptr

#22274

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    libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
    + 24
    − 17
    View file @ cd4121de
    ......@@ -101,21 +101,22 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
    SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL mm_rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
    SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL core_pll_locked : STD_LOGIC;
    SIGNAL core_pll_locked_reg : STD_LOGIC;
    SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
    SIGNAL jesd204b_sysref_1 : STD_LOGIC;
    SIGNAL jesd204b_sysref_2 : STD_LOGIC;
    SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
    ......@@ -128,7 +129,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
    SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
    SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
    SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
    SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
    -- Component declarations for the IP blocks
    ......@@ -325,9 +326,9 @@ BEGIN
    irq => open,
    clk => mm_clk, -- use clk = mm_clk for av_* port
    csr_reset => mm_rst,
    reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
    reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
    reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
    reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
    reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
    reset_in0 => mm_rst,
    reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
    reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
    ......@@ -347,8 +348,6 @@ BEGIN
    out_rst => pll_reset_arr(i)
    );
    -- No need to synchronize xcvr_rst as it is synchronized in ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
    -- synchronize rxlink reset
    u_common_areset_rxlink : ENTITY common_lib.common_areset
    PORT MAP (
    ......@@ -367,12 +366,22 @@ BEGIN
    rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
    -- synchronize rx_xcvr_ready_in_arr to mm_clk
    u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
    GENERIC MAP (
    g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
    g_rst_level => '0' -- When in_rst is asserted, out_rst = '0'
    )
    PORT MAP (
    in_rst => rx_xcvr_ready_in_arr(i),
    clk => mm_clk,
    out_rst => mm_rx_xcvr_ready_in_arr(i)
    );
    -- Invert thr active-low resets
    rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
    rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
    rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
    -----------------------------------------------------------------------------
    ......@@ -470,7 +479,7 @@ BEGIN
    PORT MAP (
    in_rst => core_pll_locked,
    clk => mm_clk,
    out_rst => core_pll_locked_reg
    out_rst => mm_core_pll_locked_reg
    );
    ......@@ -479,7 +488,7 @@ BEGIN
    u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
    PORT MAP (
    clock => rxlink_clk,
    clock => rxlink_clk,
    reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally.
    rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
    rx_cal_busy => rx_cal_busy_arr, -- input from PHY
    ......@@ -522,8 +531,6 @@ BEGIN
    mosi_arr => jesd204b_mosi_arr,
    miso_arr => jesd204b_miso_arr
    );
    END str;
    ......
    libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
    + 23
    − 17
    View file @ cd4121de
    ......@@ -101,21 +101,22 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
    SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL mm_rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
    SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
    SIGNAL core_pll_locked : STD_LOGIC;
    SIGNAL core_pll_locked_reg : STD_LOGIC;
    SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
    SIGNAL jesd204b_sysref_1 : STD_LOGIC;
    SIGNAL jesd204b_sysref_2 : STD_LOGIC;
    SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
    ......@@ -325,9 +326,9 @@ BEGIN
    irq => open,
    clk => mm_clk, -- use clk = mm_clk for av_* port
    csr_reset => mm_rst,
    reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
    reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
    reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
    reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
    reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
    reset_in0 => mm_rst,
    reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
    reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
    ......@@ -347,8 +348,6 @@ BEGIN
    out_rst => pll_reset_arr(i)
    );
    -- No need to synchronize xcvr_rst as it is synchronized in ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
    -- synchronize rxlink reset
    u_common_areset_rxlink : ENTITY common_lib.common_areset
    PORT MAP (
    ......@@ -365,14 +364,23 @@ BEGIN
    out_rst => rxframe_rst_arr(i)
    );
    rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
    -- synchronize rx_xcvr_ready_in_arr to mm_clk
    u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
    GENERIC MAP (
    g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
    g_rst_level => '0' -- When in_rst is asserted, out_rst = '0'
    )
    PORT MAP (
    in_rst => rx_xcvr_ready_in_arr(i),
    clk => mm_clk,
    out_rst => mm_rx_xcvr_ready_in_arr(i)
    );
    -- Invert thr active-low resets
    rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
    rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
    rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
    -----------------------------------------------------------------------------
    ......@@ -470,9 +478,9 @@ BEGIN
    PORT MAP (
    in_rst => core_pll_locked,
    clk => mm_clk,
    out_rst => core_pll_locked_reg
    out_rst => mm_core_pll_locked_reg
    );
    -- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
    -- Clock set to 100MHz (use rxlink_clk)
    ......@@ -522,8 +530,6 @@ BEGIN
    mosi_arr => jesd204b_mosi_arr,
    miso_arr => jesd204b_miso_arr
    );
    END str;
    ......
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