Ready for Review.

applications/lofar2/libraries/ddrctrl/hdllib.cfg

@@ -5,16 +5,16 @@ hdl_lib_uses_sim =
 hdl_lib_technology = 
 
 synth_files = 
-    src/vhdl/ddrctrl_address_counter.vhd 
-    src/vhdl/ddrctrl_pack.vhd
-    src/vhdl/ddrctrl_repack.vhd
+    src/vhdl/ddrctrl_input_address_counter.vhd 
+    src/vhdl/ddrctrl_input_pack.vhd
+    src/vhdl/ddrctrl_input_repack.vhd
     src/vhdl/ddrctrl_input.vhd
     src/vhdl/ddrctrl.vhd
 
 test_bench_files =
-    tb/vhdl/tb_ddrctrl_address_counter.vhd
-    tb/vhdl/tb_ddrctrl_pack.vhd
-    tb/vhdl/tb_ddrctrl_repack.vhd
+    tb/vhdl/tb_ddrctrl_input_address_counter.vhd
+    tb/vhdl/tb_ddrctrl_input_pack.vhd
+    tb/vhdl/tb_ddrctrl_input_repack.vhd
     tb/vhdl/tb_ddrctrl_input.vhd
     tb/vhdl/tb_ddrctrl.vhd
 

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -82,7 +82,6 @@ END ddrctrl;
 ARCHITECTURE str OF ddrctrl IS
 
   -- constant for readability
-  CONSTANT  c_out_data_w      : NATURAL       := g_nof_streams*g_data_w;    -- the input data width for ddrctrl_repack 168
   CONSTANT  c_io_ddr_data_w   : NATURAL                                     := func_tech_ddr_ctlr_data_w( g_tech_ddr );
   CONSTANT  c_wr_fifo_depth   : NATURAL                                     := 256;                                           -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
   CONSTANT  c_rd_fifo_depth   : NATURAL                                     := 256;                                           -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
@@ -94,14 +93,11 @@ ARCHITECTURE str OF ddrctrl IS
 
   -- signals for connecting the components
   SIGNAL    adr          : NATURAL                                          := 0;
-  SIGNAL    a_of         : NATURAL    := 0;
   SIGNAL    ctrl_clk     : STD_LOGIC;
   SIGNAL    ctrl_rst     : STD_LOGIC;
   SIGNAL    wr_sosi      : t_dp_sosi                                        := c_dp_sosi_init;
-  SIGNAL    wr_siso      : t_dp_siso;
-  SIGNAL    rd_siso      : t_dp_siso;
+  SIGNAL    rd_siso      : t_dp_siso                                        := c_dp_siso_rst;
   SIGNAL    dvr_mosi     : t_mem_ctlr_mosi;
-  SIGNAL    dvr_miso     : t_mem_ctlr_miso;
 
 
 BEGIN
@@ -182,7 +178,7 @@ BEGIN
     dvr_clk                   => clk,
     dvr_rst                   => rst,
     
-    dvr_miso                  => dvr_miso,
+    dvr_miso                  => open,
     dvr_mosi                  => dvr_mosi,
     
     -- Write FIFO clock domain
@@ -191,7 +187,7 @@ BEGIN
 
     wr_fifo_usedw             => open,
     wr_sosi                   => wr_sosi,
-    wr_siso                   => wr_siso,
+    wr_siso                   => open,
   
     -- Read FIFO clock domain
     rd_clk                    => clk,

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd

@@ -74,7 +74,7 @@ ARCHITECTURE str OF ddrctrl_input IS
 BEGIN
 
   -- makes one data vector out of all the data from the t_dp_sosi_arr
-  u_pack : ENTITY work.ddrctrl_pack
+  u_pack : ENTITY work.ddrctrl_input_pack
   GENERIC MAP(
 
     g_nof_streams     => g_nof_streams,                                 -- number of input streams
@@ -89,7 +89,7 @@ BEGIN
   );
 
   -- resizes the input data vector so that the output data vector can be stored into the ddr memory
-  u_repack : ENTITY work.ddrctrl_repack
+  u_repack : ENTITY work.ddrctrl_input_repack
   GENERIC MAP(
     g_tech_ddr        => g_tech_ddr,                                    -- type of memory
     g_in_data_w       => c_out_data_w                                   -- the input data with
@@ -103,7 +103,7 @@ BEGIN
   );
 
   -- creates address by counting input valids
-  u_address_counter : ENTITY work.ddrctrl_address_counter
+  u_address_counter : ENTITY work.ddrctrl_input_address_counter
   GENERIC MAP(
     g_tech_ddr        => g_tech_ddr,                                    -- type of memory
     g_sim_model       => g_sim_model                                    -- determens if this is a simulation

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd → applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd

@@ -39,7 +39,7 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 
-ENTITY ddrctrl_address_counter IS
+ENTITY ddrctrl_input_address_counter IS
   GENERIC (
     g_tech_ddr            : t_c_tech_ddr;                                                                                                 -- type of memory
     g_sim_model           : BOOLEAN                               := TRUE                                                                 -- determens if this is a simulation
@@ -53,10 +53,10 @@ ENTITY ddrctrl_address_counter IS
     out_of                : OUT NATURAL;
     out_adr               : OUT NATURAL
   );
-END ddrctrl_address_counter;
+END ddrctrl_input_address_counter;
 
 
-ARCHITECTURE rtl OF ddrctrl_address_counter IS
+ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
 
   -- constants for readability
   CONSTANT c_data_w       : NATURAL                               := func_tech_ddr_ctlr_data_w( g_tech_ddr );                             -- the with of the input data and output data, 576

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd → applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd

@@ -31,7 +31,7 @@ LIBRARY IEEE, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
-ENTITY ddrctrl_pack IS
+ENTITY ddrctrl_input_pack IS
   GENERIC (
 
     g_nof_streams : POSITIVE := 12;                                           -- number of input streams
@@ -44,9 +44,9 @@ ENTITY ddrctrl_pack IS
     out_data      : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
 
   );
-END ddrctrl_pack;
+END ddrctrl_input_pack;
 
-ARCHITECTURE rtl OF ddrctrl_pack IS
+ARCHITECTURE rtl OF ddrctrl_input_pack IS
 
 BEGIN
 

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd → applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd

@@ -34,7 +34,7 @@ USE IEEE.std_logic_1164.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
 
-ENTITY ddrctrl_repack IS
+ENTITY ddrctrl_input_repack IS
   GENERIC (
     g_tech_ddr              : t_c_tech_ddr;                                                                                                   -- type of memory
     g_in_data_w             : NATURAL       := 168                                                                                            -- the input data with
@@ -46,10 +46,10 @@ ENTITY ddrctrl_repack IS
     out_of                  : OUT NATURAL   := 0;                                                                                             -- amount of internal overflow this output
     out_sosi                : OUT t_dp_sosi := c_dp_sosi_init                                                                                 -- output data
   );
-END ddrctrl_repack;
+END ddrctrl_input_repack;
 
 
-ARCHITECTURE rtl OF ddrctrl_repack IS
+ARCHITECTURE rtl OF ddrctrl_input_repack IS
 
   -- constant for readability
   CONSTANT c_out_data_w     : NATURAL       := func_tech_ddr_ctlr_data_w( g_tech_ddr );                                                       -- the output data with, 576

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd

@@ -40,7 +40,7 @@ ENTITY tb_ddrctrl IS
     g_sim_model               : BOOLEAN                                               := TRUE;                                    -- determens if this is a simulation
     g_nof_streams             : POSITIVE                                              := 12;                                      -- number of input streams
     g_data_w                  : NATURAL                                               := 14;                                      -- data with of input data vectors
-    g_sim_length              : NATURAL                                               := 16500;
+    g_sim_length              : NATURAL                                               := 16500;                                   -- close to the amount of word that gets put into the memory
     g_technology              : NATURAL                                               := c_tech_select_default;
     g_tech_ddr3               : t_c_tech_ddr                                          := c_tech_ddr3_4g_800m_master;
     g_tech_ddr4               : t_c_tech_ddr                                          := c_tech_ddr4_4g_1600m
@@ -52,30 +52,27 @@ ARCHITECTURE tb OF tb_ddrctrl IS
   -- constants for testbench
   CONSTANT  c_clk_freq        : NATURAL                                               := 200;                                     -- clock frequency in MHz
   CONSTANT  c_clk_period      : TIME                                                  := (10**6 / c_clk_freq) * 1 ps;             -- clock priod, 5 ns
-  CONSTANT  c_mm_clk_freq     : NATURAL                                               := 100;
-  CONSTANT  c_mm_clk_period   : TIME                                                  := (10**6 / c_mm_clk_freq) * 1 ps;
-  CONSTANT  c_sim_length      : NATURAL                                               := (g_sim_length*576)/168;
+  CONSTANT  c_mm_clk_freq     : NATURAL                                               := 100;                                     -- mm clock frequency in MHz
+  CONSTANT  c_mm_clk_period   : TIME                                                  := (10**6 / c_mm_clk_freq) * 1 ps;          -- mm clock period, 10 ns
+  CONSTANT  c_sim_length      : NATURAL                                               := (g_sim_length*576)/168;                  -- amount of input words that get put into the DUT
 
   -- Select DDR3 or DDR4 dependent on the technology and sim model
   CONSTANT c_mem_ddr          : t_c_tech_ddr                                          := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
   CONSTANT c_sim_ddr          : t_c_tech_ddr                                          := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
   CONSTANT c_tech_ddr         : t_c_tech_ddr                                          := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
 
-  CONSTANT c_wr_fifo_depth            : NATURAL := 16;  -- defined at DDR side of the FIFO 
-  CONSTANT c_rd_fifo_depth            : NATURAL := 256;  -- defined at DDR side of the FIFO 
   
   -- constants for readability
   CONSTANT  c_in_data_w       : NATURAL                                               := g_nof_streams * g_data_w;                -- output data with, 168
-  CONSTANT  c_out_data_w      : NATURAL                                               := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
-  CONSTANT  c_adr_w           : NATURAL                                               := 4;                                       -- address with in simulation
-  CONSTANT  c_adr_size        : NATURAL                                               := 2**c_adr_w;                              -- address size in simulation
 
   -- function for making total data vector
   FUNCTION  c_total_vector_init RETURN STD_LOGIC_VECTOR IS
     VARIABLE temp             : STD_LOGIC_VECTOR(c_in_data_w*c_sim_length-1 DOWNTO 0);
+    VARIABLE conv             : STD_LOGIC_VECTOR(32-1 DOWNTO 0);                                                                  -- removes a warning
   BEGIN
     FOR I IN 0 TO c_sim_length*g_nof_streams-1 LOOP
-      temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
+      conv                                     := TO_UVEC(I, 32);
+      temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := conv(g_data_w-1 DOWNTO 0);
     END LOOP;
     RETURN temp;
   END FUNCTION c_total_vector_init;
@@ -89,27 +86,16 @@ ARCHITECTURE tb OF tb_ddrctrl IS
   SIGNAL    rst               : STD_LOGIC                                             := '0';
   SIGNAL    mm_clk            : STD_LOGIC                                             := '0';
   SIGNAL    mm_rst            : STD_LOGIC                                             := '0';
-  SIGNAL    q_rst             : STD_LOGIC                                             := '0';
-  SIGNAL    q_q_rst           : STD_LOGIC                                             := '0';
   SIGNAL    in_sosi_arr       : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)               := (OTHERS => c_dp_sosi_init);              -- input data signal for ddrctrl_pack.vhd 
   SIGNAL    wr_not_rd         : STD_LOGIC;
 
-  -- output singals from ddrctrl.vhd
-  SIGNAL    out_of            : NATURAL                                               := 0;                                       -- output signal from ddrctrl_repack to determen how high the overflow is
-  SIGNAL    out_adr           : NATURAL                                               := 0;
 
   -- testbench signal
   SIGNAL    tb_end            : STD_LOGIC                                             := '0';                                     -- signal to turn the testbench off
 
   -- signals for running test
   SIGNAL    in_data_cnt       : NATURAL                                               := 0;                                       -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
-  SIGNAL    q_in_data_cnt     : NATURAL                                               := 0;                                       -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 1 clockcycle
-  SIGNAL    q_q_in_data_cnt   : NATURAL                                               := 0;                                       -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 2 clockcycles
   SIGNAL    test_running      : STD_LOGIC                                             := '0';                                     -- signal to tell wheter the testing has started
-  SIGNAL    q_test_running    : STD_LOGIC                                             := '0';                                     -- signal to tell wheter the testing has started with a delay of 1 clockcycle
-  SIGNAL    q_q_test_running  : STD_LOGIC                                             := '0';                                     -- signal to tell wheter the testing has started with a delay of 2 clockcycles
-  SIGNAL    lag_due_reset     : NATURAL                                               := 0;                                       -- signal to hold the address lag after a rest
-  SIGNAL    q_lag_due_reset   : NATURAL                                               := 0;                                       -- signal to hold the address lag after a rest with a delay of 1 clockcycle
 
   -- PHY
   SIGNAL    phy3_io           : t_tech_ddr3_phy_io;
@@ -159,15 +145,6 @@ BEGIN
     test_running      <= '0';
     wr_not_rd         <= '0';
 
-    -- testing reset
---    FOR I IN 0 TO c_sim_length-1 LOOP
---      rst <= '1';
---      WAIT FOR c_clk_period*1;
---      rst <= '0';
---      WAIT FOR c_clk_period*((((c_out_data_w/c_in_data_w)+1)*c_adr_size)+4);
---    END LOOP;
-
-
     -- stopping the testbench
     WAIT FOR c_clk_period*4;
     tb_end <= '1';
@@ -193,8 +170,8 @@ BEGIN
     mm_rst            => mm_rst,
     in_sosi_arr       => in_sosi_arr,
     wr_not_rd         => wr_not_rd,
-    out_of            => out_of,
-    out_adr           => out_adr,
+    out_of            => open,
+    out_adr           => open,
 
     --PHY
     phy3_io           => phy3_io,

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd → applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd

@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 -- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_address_counter.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_address_counter.vhd
 -- Usage:
 -- > run -a
 
@@ -30,7 +30,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 
-ENTITY tb_ddrctrl_address_counter IS
+ENTITY tb_ddrctrl_input_address_counter IS
   GENERIC (
     
     g_tech_ddr                : t_c_tech_ddr    := c_tech_ddr4_8g_1600m;                    -- type of memory
@@ -38,9 +38,9 @@ ENTITY tb_ddrctrl_address_counter IS
     g_sim_length              : NATURAL         := 52                                       -- determens the length of the duration of the test
 
   );
-END tb_ddrctrl_address_counter;
+END tb_ddrctrl_input_address_counter;
 
-ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
+ARCHITECTURE tb OF tb_ddrctrl_input_address_counter IS
 
   -- constants for running the testbench
   CONSTANT  c_clk_freq        : NATURAL         := 200;                                     -- clock frequency in MHz
@@ -189,7 +189,7 @@ BEGIN
 
 
   -- DUT
-  u_ddrctrl_address_counter : ENTITY work.ddrctrl_address_counter
+  u_ddrctrl_input_address_counter : ENTITY work.ddrctrl_input_address_counter
   GENERIC MAP (
     g_tech_ddr        => g_tech_ddr,
     g_sim_model       => g_sim_model

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd → applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_pack.vhd

@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 -- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_pack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_pack.vhd
 -- Usage:
 -- > run -a
 
@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 
-ENTITY tb_ddrctrl_pack IS
+ENTITY tb_ddrctrl_input_pack IS
   GENERIC (
 
     g_nof_streams             : POSITIVE                                    := 12;                                -- number of input streams
@@ -40,9 +40,9 @@ ENTITY tb_ddrctrl_pack IS
     g_sim_length              : NATURAL                                     := 52                                 -- determens the lengt of the duration of the test
 
  );
-END tb_ddrctrl_pack;
+END tb_ddrctrl_input_pack;
 
-ARCHITECTURE tb OF tb_ddrctrl_pack IS
+ARCHITECTURE tb OF tb_ddrctrl_input_pack IS
 
   -- constants for running the testbench
   CONSTANT  c_clk_freq        : NATURAL                                     := 200;                               -- clock frequency in MHz
@@ -123,7 +123,7 @@ BEGIN
   END PROCESS;
 
   -- DUT
-  u_ddrctrl_pack : ENTITY work.ddrctrl_pack
+  u_ddrctrl_input_pack : ENTITY work.ddrctrl_input_pack
   GENERIC MAP (
     g_nof_streams     => g_nof_streams,
     g_data_w          => g_data_w

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd → applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_repack.vhd

@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 -- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_repack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_repack.vhd
 -- Usage:
 -- > run -a
 
@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 
-ENTITY tb_ddrctrl_repack IS
+ENTITY tb_ddrctrl_input_repack IS
   GENERIC (
 
     g_tech_ddr                : t_c_tech_ddr                                           := c_tech_ddr4_8g_1600m;                    -- type of memory
@@ -40,9 +40,9 @@ ENTITY tb_ddrctrl_repack IS
     g_sim_lengt               : NATURAL                                                := 52                                       -- amount of times there wil be input data for ddrctrl_repack in this testbench
 
   );
-END tb_ddrctrl_repack;
+END tb_ddrctrl_input_repack;
 
-ARCHITECTURE tb OF tb_ddrctrl_repack IS
+ARCHITECTURE tb OF tb_ddrctrl_input_repack IS
 
   -- constants for running testbench
   CONSTANT  c_clk_freq        : NATURAL                                                := 200;                                     -- clock freqency in MHz
@@ -134,7 +134,7 @@ BEGIN
 
 
   -- DUT
-  u_ddrctrl_repack : ENTITY work.ddrctrl_repack
+  u_ddrctrl_input_repack : ENTITY work.ddrctrl_input_repack
   GENERIC MAP (
     g_tech_ddr        => g_tech_ddr,
     g_in_data_w       => g_in_data_w