Renamed tx_clk to tx_clk_156 and rx_clk to rx_clk_156

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -501,12 +501,12 @@ BEGIN
         csr_miso         => reg_mac_miso_arr(i),
       
         -- ST
-        tx_clk           => tx_clk_arr(i),           -- 156.25 MHz local reference
+        tx_clk_156       => tx_clk_arr(i),           -- 156.25 MHz local reference
         tx_rst           => tx_rst_arr(i),
         tx_snk_in        => mac_10g_snk_in_arr(i),   -- 64 bit data
         tx_snk_out       => mac_10g_snk_out_arr(i),
         
-        rx_clk           => rx_clk_arr(i),           -- 156.25 MHz from rx phy
+        rx_clk_156       => rx_clk_arr(i),           -- 156.25 MHz from rx phy
         rx_rst           => rx_rst_arr(i),
         rx_src_out       => mac_10g_src_out_arr(i),  -- 64 bit data
         rx_src_in        => mac_10g_src_in_arr(i), 

libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd

@@ -259,12 +259,12 @@ BEGIN
       csr_miso         => mm_miso,
   
       -- ST
-      tx_clk           => tx_ref_clk,     -- 156.25 MHz local reference
+      tx_clk_156       => tx_ref_clk,     -- 156.25 MHz local reference
       tx_rst           => tx_rst,
       tx_snk_in        => tx_sosi,        -- 64 bit data
       tx_snk_out       => tx_siso, 
       
-      rx_clk           => rx_phy_clk,     -- 156.25 MHz from rx phy
+      rx_clk_156       => rx_phy_clk,     -- 156.25 MHz from rx phy
       rx_rst           => rx_rst,
       rx_src_out       => rx_sosi,        -- 64 bit data
       rx_src_in        => rx_siso,