Change dvr_wr_fifo_usedw into more appropriate wr_fifo_usedw in wr_clk domain.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -43,14 +43,13 @@
 --
 -- Block diagram:
 --
---   dvr_wr_fifo_usedw <-*-------------------\
---                                           |
---                        ctlr_wr_fifo_src   |    ctlr_wr_snk   ctlr_mosi
---                                    .      |      .             .
---                      ________      .      |      .   _______   .   ______
---                     |        |-----.------+------.->|       |  .  |      |
+--
+--                        ctlr_wr_fifo_src        ctlr_wr_snk   ctlr_mosi
+--                                    .             .             .
+--                      ________      .             .   _______   .   ______
+--                     |        |-----.-------------.->|       |  .  |      |
 --                     |        |     .   ______    .  |       |  .  |      |
---                     |dp_fifo |     .  |      |   .  |       |  .  |      |
+--   wr_fifo_usedw <---|dp_fifo |     .  |      |   .  |       |  .  |      |
 --   wr_sosi --------->|dc_mixed|-+----->|dp    |----->| io    |  .  | tech |
 --   wr_clk  --------->|widths  | |      |flush |      | ddr   |  .  | ddr  |
 --                     |________| |      |______|<--\  | driver|  .  |      |
@@ -71,7 +70,7 @@
 --                      ________                       |       |  .  |      |
 --   rd_clk  --------->|dp_fifo |                      |       |  .  |      |
 --   rd_sosi <---------|dc_mixed|<---------------------|       |  .  |      |
---   rd_fifo_usedw     |widths  |                   .  |_______|  .  |______|---\
+--   rd_fifo_usedw <---|widths  |                   .  |_______|  .  |______|---\
 --                     |________|                   .             .             |
 --                                                ctlr_rd_src   ctlr_miso       |
 --                                                              ctlr_init_done  |
@@ -86,8 +85,7 @@
 --   to wires. However dvr_clk could also be the dp_clk or the mm_clk and then 
 --   the clock domain crossing logic is needed.
 --   No need to cross dvr_start_addr, because the address is stable when the
---   dvr_en is stable. No need to cross dvr_wr_fifo_usedw, because it is only
---   used for monitoring purposes.
+--   dvr_en is stable.
 -- . Externally connect ctlr_clk = ctlr_clk_in = ctlr_clk_out
 -- . Typically wr_clk = rd_clk = dp_clk.
 -- . The main PHY signals are carried by phy_ou and phy_io. The phy_in signals
@@ -136,12 +134,12 @@ ENTITY io_ddr IS
     dvr_start_addr     : IN    t_tech_ddr_addr;
     dvr_end_addr       : IN    t_tech_ddr_addr;
     dvr_wr_flush_en    : IN    STD_LOGIC := '0';
-    dvr_wr_fifo_usedw  : OUT   STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_wr_data_w) )-1 DOWNTO 0);  -- for monitoring purposes
 
     -- Write FIFO clock domain
     wr_clk             : IN    STD_LOGIC;
     wr_rst             : IN    STD_LOGIC;
 
+    wr_fifo_usedw      : OUT   STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_wr_data_w) )-1 DOWNTO 0);  -- for monitoring purposes
     wr_sosi            : IN    t_dp_sosi;
     wr_siso            : OUT   t_dp_siso;
   
@@ -149,11 +147,10 @@ ENTITY io_ddr IS
     rd_clk             : IN    STD_LOGIC;
     rd_rst             : IN    STD_LOGIC;
     
+    rd_fifo_usedw      : OUT   STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);    
     rd_sosi            : OUT   t_dp_sosi;
     rd_siso            : IN    t_dp_siso;
     
-    rd_fifo_usedw      : OUT   STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);    
-
     -- DDR PHY external interface
     phy_in             : IN    t_tech_ddr_phy_in;
     phy_io             : INOUT t_tech_ddr_phy_io;
@@ -220,7 +217,6 @@ BEGIN
     dvr_start_addr         => dvr_start_addr,
     dvr_end_addr           => dvr_end_addr,
     dvr_wr_flush_en        => dvr_wr_flush_en,
-    dvr_wr_fifo_usedw      => dvr_wr_fifo_usedw,
     
     -- DDR controller clock domain
     ctlr_clk               => ctlr_clk_in,
@@ -231,8 +227,7 @@ BEGIN
     ctlr_dvr_wr_not_rd     => ctlr_dvr_wr_not_rd,
     ctlr_dvr_start_addr    => ctlr_dvr_start_addr,
     ctlr_dvr_end_addr      => ctlr_dvr_end_addr,
-    ctlr_dvr_wr_flush_en   => ctlr_dvr_wr_flush_en,
-    ctlr_dvr_wr_fifo_usedw => ctlr_wr_fifo_usedw
+    ctlr_dvr_wr_flush_en   => ctlr_dvr_wr_flush_en
   );
    
   p_wr_fifo_snk_in : PROCESS (wr_sosi)
@@ -263,7 +258,7 @@ BEGIN
     snk_out        => wr_siso,
     snk_in         => wr_fifo_snk_in,
   
-    wr_usedw       => OPEN,
+    wr_usedw       => wr_fifo_usedw,
     rd_usedw       => ctlr_wr_fifo_usedw,
     rd_emp         => OPEN,
 

libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd

@@ -28,8 +28,7 @@
 --   to wires. However dvr_clk could also be the dp_clk or the mm_clk and then 
 --   the clock domain crossing logic is needed.
 --   No need to cross dvr_start_addr, because the address is stable when the
---   dvr_en is stable. No need to cross dvr_wr_fifo_usedw, because it is only
---   used for monitoring purposes.
+--   dvr_en is stable.
         
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -54,7 +53,6 @@ ENTITY io_ddr_cross_domain IS
     dvr_start_addr         : IN  t_tech_ddr_addr;
     dvr_end_addr           : IN  t_tech_ddr_addr;
     dvr_wr_flush_en        : IN  STD_LOGIC := '0';
-    dvr_wr_fifo_usedw      : OUT STD_LOGIC_VECTOR;
     
     -- DDR controller clock domain
     ctlr_clk               : IN  STD_LOGIC;
@@ -65,9 +63,8 @@ ENTITY io_ddr_cross_domain IS
     ctlr_dvr_wr_not_rd     : OUT STD_LOGIC;
     ctlr_dvr_start_addr    : OUT t_tech_ddr_addr;
     ctlr_dvr_end_addr      : OUT t_tech_ddr_addr;
-    ctlr_dvr_wr_flush_en   : OUT STD_LOGIC := '0';
-    ctlr_dvr_wr_fifo_usedw : IN  STD_LOGIC_VECTOR
-   );
+    ctlr_dvr_wr_flush_en   : OUT STD_LOGIC := '0'
+  );
 END io_ddr_cross_domain;
 
 
@@ -88,7 +85,6 @@ BEGIN
     
     -- ctlr_clk --> dvr_clk
     dvr_done               <= ctlr_dvr_done;
-    dvr_wr_fifo_usedw      <= ctlr_dvr_wr_fifo_usedw;
   END GENERATE;
   
   gen_cross : IF g_cross_domain=TRUE GENERATE
@@ -141,9 +137,6 @@ BEGIN
     -- Ensure previous dvr_done goes low after new dvr_en
     dvr_done <= new_dvr_done AND NOT dvr_en_busy;
       
-    -- Only register the word in the other clock domai 
-    dvr_wr_fifo_usedw <= ctlr_dvr_wr_fifo_usedw WHEN rising_edge(ctlr_clk);
-    
   END GENERATE;
   
 END str;