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Commit cb41e048 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-854' into 'master'

added 16G ddr4 IP and created example design.

Closes L2SDP-854

See merge request desp/hdl!290
parents e6769e2e 01fad539
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1 merge request!290added 16G ddr4 IP and created example design.
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#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600/sim"
vcom "$IP_DIR/ip_arria10_e2sg_ddr4_16g_1600.vhd"
#------------------------------------------------------------------------------
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
#file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
#file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
#file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
#file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
file copy -force $IP_DIR/../altera_avalon_onchip_memory2_1920/sim/seq_cal_soft_m20k.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_191_qssf3hq_seq_cal.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_191_qssf3hq_seq_params_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_altera_emif_arch_nf_191_qssf3hq_seq_params_synth.hex ./
}
hdl_lib_name = ip_arria10_e2sg_ddr4_16g_1600
hdl_library_clause_name = ip_arria10_e2sg_ddr4_16g_1600_altera_emif_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_emif_1910 ip_arria10_e2sg_altera_merlin_master_translator_191
hdl_lib_technology = ip_arria10_e2sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600/ip_arria10_e2sg_ddr4_16g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_ddr4_16g_1600.ip
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