Use common_async go g_tree_len.

libraries/base/common/src/vhdl/common_areset.vhd

@@ -22,15 +22,30 @@
 -- Author: E. Kooistra
 -- Purpose: Immediately apply reset and synchronously release it at rising clk
 -- Description:
---   When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply).
---   When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous
---   reset release) + g_tree_len cycles (synchronous reset tree).
+--   When in_rst gets asserted, then the out_rst gets asserted immediately (=
+--   asynchronous reset apply).
+--   When in_rst gets de-assered, then out_rst gets de-asserted after
+--   g_delay_len cycles (= synchronous reset release) + g_tree_len cycles
+--   (synchronous reset tree).
 --
 --   The in_rst assert level is set by g_in_rst_level.
 --   The out_rst assert level is set by c_out_rst_level = g_rst_level.
 --
+-- * g_delay_len: Long enough to ensure that the o_rst output of u_async has
+--   recovered from meta-stability that can occur when a flipflop (FF) clocks
+--   in the asynchrounous in_rst while it changes level.
+-- * g_tree_len:
+--   . Use g_tree_len = 0 to only have u_async, so with asynchrounous path from
+--     in_rst to out_rst.
+--   . Use g_tree_len = 1 to only have u_pipe of one flipflop (FF) to break the
+--     asynchronous path, but with only one clk cycle extra latency.
+--   . Use g_tree_len = c_tree_delay_len >> 1 to have a multi stage FF delay
+--     line that can be expanded into a synchronous reset tree by means of FF
+--     register duplication by the synthesis tool. The multi stage register
+--     duplication eases timing closure in case of large fanout for out_rst.
 -- Remarks:
--- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
+-- . The in_rst can also synchronise other signals than a reset, e.g. a locked
+--   signal from a PLL.
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -42,7 +57,7 @@ entity common_areset is
     g_rst_level    : std_logic := '1';  -- = out_rst level (keep original generic
                                         --   name for backward compatibility)
     g_delay_len    : natural := c_meta_delay_len;
-    g_tree_len     : natural := c_tree_delay_len
+    g_tree_len     : natural := 1
   );
   port (
     in_rst    : in  std_logic;
@@ -82,15 +97,21 @@ begin
   -- combinatorial path with in_rst to ease timing closure in the reset tree
   -- network. Use g_tree_len = 0 for wire out_rst <= o_rst, so no reset tree
   -- as in 2009.
-  u_pipe : entity work.common_pipeline_sl
-  generic map (
-    g_pipeline    => g_tree_len,
-    g_reset_value => c_out_rst_value
-  )
-  port map (
-    rst     => '0',
-    clk     => clk,
-    in_dat  => o_rst,
-    out_dat => out_rst
-  );
+  no_pipe : if g_tree_len = 0 generate
+    out_rst <= o_rst;  -- wires
+  end generate;
+
+  gen_pipe : if g_tree_len > 0 generate
+    u_pipe : entity work.common_async
+    generic map (
+      g_rst_level => c_out_rst_level,
+      g_delay_len => g_tree_len  -- must be positive in common_async
+    )
+    port map (
+      rst  => '0',
+      clk  => clk,
+      din  => o_rst,
+      dout => out_rst
+    );
+  end generate;
 end str;