Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

H

HDL
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Iterations
- Wiki
- Requirements
- Jira
- Environments
- Incidents

Snippets Groups Projects

cace6663

Commit cace6663 authored 9 years ago by Zanting

Downloads
- Patches
- Plain Diff

IP for 16GB DDR3 So-Dimm modules

parent 5d9e7979

No related branches found

No related tags found

Loading

Changes 5

Hide whitespace changes

Inline Side-by-side

Showing

libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl 155 additions, 0 deletions

...y/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl 32 additions, 0 deletions

..._stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh 50 additions, 0 deletions

...y/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generate_ip.sh
libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg 17 additions, 0 deletions

...ology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v 390 additions, 0 deletions

..._dual_rank_800/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v

with 644 additions and 0 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment