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Commit ca4835e2 authored by Eric Kooistra's avatar Eric Kooistra
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Changed ip_arria10 into ip_arria10_e3sge3 using a text editor.

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README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
Contents: See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
1) Porting
2) IP component
3) Compilation, simulation and verification
4) Synthesis
5) Remarks
1) Porting
The tse_sgmii_lvds IP was ported manually from Quartus v9.1 for Stratix IV to Quartus 14.0a10 for Arria10 by creating it in Qsys using
the same parameter settings.
2) IP component
The generated IP is not kept in SVN, only the Qsys source file:
ip/ip_arria10_tse_sgmii_lvds.qsys
Therefore first the IP needs to be generated using:
ip/generate_ip.sh
3) Compilation, simulation and verification
The genrated IP also contains a msim_setup.tcl file that was used to manually create:
ip/compile_ip.tcl
This ip/compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
The IP can be verified with the self checking test bench:
tb_ip_arria10_tse_sgmii_lvds_top.vhd
This test bench is functionally identical to tb_ip_stratixiv_tse_sgmii_lvds.vhd, but instead it instantiates the ip_arria10_tse_sgmii_lvds.vhd
component as DUT.
4) Synthesis
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
ip/generated/ip_arria10_tse_sgmii_lvds.qip
is included in the ip/hdllib.cfg and contains what is needed to synthesize the IP.
5) Remarks
a) Use generated IP specific library clause name
The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library claus name to make it known:
hdl_lib_name = ip_arria10_<lib_name>
hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
b) Generated IP uses several more libraries
The generated IP uses several more libraries. Just as the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library
these other libraries are all mapped to ./work in ip/compile_ip.tcl.
\ No newline at end of file
...@@ -37,14 +37,14 @@ ...@@ -37,14 +37,14 @@
# Only generate the source IP # Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard # - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_tse_sgmii_lvds.qsys \ qsys-generate ip_arria10_e3sge3_tse_sgmii_lvds.qsys \
--synthesis=VHDL \ --synthesis=VHDL \
--simulation=VHDL \ --simulation=VHDL \
--output-directory=generated \ --output-directory=generated \
--allow-mixed-language-simulation --allow-mixed-language-simulation
# Also generate the testbench IP # Also generate the testbench IP
#qsys-generate ip_arria10_tse_sgmii_lvds.qsys \ #qsys-generate ip_arria10_e3sge3_tse_sgmii_lvds.qsys \
# --synthesis=VHDL \ # --synthesis=VHDL \
# --simulation=VHDL \ # --simulation=VHDL \
# --testbench=STANDARD \ # --testbench=STANDARD \
......
hdl_lib_name = ip_arria10_tse_sgmii_lvds hdl_lib_name = ip_arria10_e3sge3_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_150 hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_150
hdl_lib_uses_synth = common hdl_lib_uses_synth = common
hdl_lib_uses_sim = hdl_lib_uses_sim =
...@@ -11,8 +11,8 @@ modelsim_compile_ip_files = ...@@ -11,8 +11,8 @@ modelsim_compile_ip_files =
synth_files = synth_files =
test_bench_files = test_bench_files =
tb_ip_arria10_tse_sgmii_lvds.vhd tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
quartus_qip_files = quartus_qip_files =
generated/ip_arria10_tse_sgmii_lvds.qip generated/ip_arria10_e3sge3_tse_sgmii_lvds.qip
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Purpose: Testbench for ip_arria10_tse_sgmii_lvds. -- Purpose: Testbench for ip_arria10_e3sge3_tse_sgmii_lvds.
-- Description: -- Description:
-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is -- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
-- generated by the MegaWizard provides an elaborate testbench. For -- generated by the MegaWizard provides an elaborate testbench. For
...@@ -38,11 +38,11 @@ USE IEEE.numeric_std.ALL; ...@@ -38,11 +38,11 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
ENTITY tb_ip_arria10_tse_sgmii_lvds IS ENTITY tb_ip_arria10_e3sge3_tse_sgmii_lvds IS
END tb_ip_arria10_tse_sgmii_lvds; END tb_ip_arria10_e3sge3_tse_sgmii_lvds;
ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_lvds IS ARCHITECTURE tb OF tb_ip_arria10_e3sge3_tse_sgmii_lvds IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
...@@ -631,8 +631,8 @@ BEGIN ...@@ -631,8 +631,8 @@ BEGIN
WAIT; WAIT;
END PROCESS; END PROCESS;
dut : ENTITY work.ip_arria10_tse_sgmii_lvds dut : ENTITY work.ip_arria10_e3sge3_tse_sgmii_lvds
-- The ip_arria10_tse_sgmii_lvds needs to be regenerated if its parameters are changed. -- The ip_arria10_e3sge3_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
-- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
......
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