Renamed component to entity

tools/oneclick/prestudy/components/components.py

@@ -7,6 +7,7 @@ import sys
 import os
 import os.path
 import shutil
+import mmm_config
 
 # FIXME - We have a weird discrepancy here:
 #         - user can connect components to components
@@ -148,7 +149,7 @@ class Port(object):
             self.pipe_end  = src_end
             other.pipe_end = snk_end
 
-        return Connection( (self.component_name, self.name), (other.component_name, other.name) )
+        return Connection( (self.entity_name, self.name), (other.entity_name, other.name) )
 
     def send(self, item):
         self.pipe_end.send(item) 
@@ -162,16 +163,16 @@ class Port(object):
 
 class Connection():
     def __init__(self, src, snk):
-        self.src_component_name = src[0]
+        self.src_entity_name = src[0]
         self.src_port_name = src[1]
-        self.snk_component_name = snk[0]
+        self.snk_entity_name = snk[0]
         self.snk_port_name = snk[1]
-        self.vhdl_assignment_left  = self.snk_component_name + '_' + self.snk_port_name
-        self.vhdl_assignment_right = self.src_component_name + '_' + self.src_port_name
+        self.vhdl_assignment_left  = self.snk_entity_name + '_' + self.snk_port_name
+        self.vhdl_assignment_right = self.src_entity_name + '_' + self.src_port_name
         self.vhdl_assignment_operator =  '<=' 
         self.vhdl_assignment = self.vhdl_assignment_left + ' ' + self.vhdl_assignment_operator + ' ' + self.vhdl_assignment_right + ';\n'
 
-class Component(mp.Process):  
+class Entity(mp.Process):  
     s_port_start        = "  PORT (\n"
     s_port_map_start    = "  PORT MAP(\n"
     s_generic_start     = "  GENERIC (\n"
@@ -194,6 +195,8 @@ class Component(mp.Process):
         self.longestGenericName = 1  
         self.longestGenericType = 1 
         
+#        print components
+        
         if components:
             self.architecture = Architecture('arch_' + self.name, components, connections)
         
@@ -433,7 +436,7 @@ class Component(mp.Process):
             elif i.type == "STD_LOGIC_VECTOR(0 DOWNTO 0)":
                 i.type = "STD_LOGIC"
 
-    def start_components(self):
+    def start_entities(self):
         if self.components == []:
             # This is not a composite component but a base component, start this instance itself
             self.start()
@@ -441,9 +444,9 @@ class Component(mp.Process):
             # This is a composite component, start the internal instances
             for component in self.components:
                 print 'Starting', component
-                component.start_components()
+                component.start_entities()
 
-    def terminate_components(self):
+    def terminate_entities(self):
         if self.components == []:
             # This is not a composite component but a base component, terminate this instance itself
             self.terminate()
@@ -451,12 +454,12 @@ class Component(mp.Process):
             # This is a composite component, terminate the internal instances
             for component in self.components:
                 print 'Terminating', component
-                component.terminate_components()
+                component.terminate_entities()
 
     def run_time(self, time_sec):
-        self.start_components()
+        self.start_entities()
         time.sleep(time_sec)
-        self.terminate_components()
+        self.terminate_entities()
     
 
     def get_vhdl_instance(self):
@@ -528,19 +531,24 @@ class Architecture(object):
         self.components = components
         self.connections = connections
         self.temp_connections = []
+        self.mm_regs = []
 
 
         self.constants           = []
         self.signals             = [] 
-        self.components          = []  
         self.longestConstantName = 0   
         self.longestConstantType = 0   
         self.longestSignalName   = 0   
         self.longestSignalType   = 0   
 
     def generate(self, target_vhdl_file=None):   
+        print "Generate" 
         if self.components != []: # Sub-components determine the contents of this generated file (e.g. top level)    
-            target_vhdl_file = open(self.vhdl_file_name, "w")                                                     
+#            target_vhdl_file = open(self.vhdl_file_name, "w")
+            
+            for component in self.components: 
+                for registerSpan in component.mm_regs:
+                    self.mm_regs.append(registerSpan)
             
     def add_constant(self, name, type, value = ""): 
         newConstant = Constant(name, type, value)
@@ -608,3 +616,47 @@ class Architecture(object):
             signalTypes.append(self.signals[i].type)
         self.longestSignalType = len(max(signalTypes, key=len))
 
+class MmmEntity(Entity): 
+    
+    def __init__(self, name, slave_components, synth_master = 'QSYS'):
+        Entity.__init__(self, name)
+        self.slave_components = slave_components
+        self.synth_master = 'QSYS'
+        self.mmmconfig = mmm_config.MmmConfig(mmmLibraryName = name)
+        
+        # Create mmm_conf dictionary based on included slave components. 
+        if self.slave_components != []: # Sub-components determine the contents of this generated file (e.g. top level)    
+            for component in self.slave_components: 
+                for registerSpan in component.mm_regs:
+                    self.mmmconfig.add_peripheral(registerSpan)
+            
+            for registerSpan in self.mmmconfig.peripherals:
+                print registerSpan 
+        
+        # Add default generics
+        self.add_generic( "g_sim",         "BOOLEAN", "FALSE")
+        self.add_generic( "g_sim_unb_nr",  "NATURAL", "0")
+        self.add_generic( "g_sim_node_nr", "NATURAL", "0")
+        
+        # Add input clks
+        if "mm_clk" in self.mmmconfig.input_clks:
+            self.add_port("mm_clk",     "IN", "STD_LOGIC", "\'1\'")      
+            self.add_port("mm_rst",     "IN", "STD_LOGIC", "\'1\'")              
+        
+        # Add UNB1 board peripherals
+        for s in self.mmmconfig.peripherals:   
+            
+            # Extra signals for ethernet peripheral
+            if(s[0] == "eth1g_ram"): 
+                #self.add_port("eth1g_tse_clk",       "OUT", "STD_LOGIC")      
+                self.add_port("eth1g_mm_rst",        "OUT", "STD_LOGIC")    
+                self.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")   
+            
+            # Extra signal for Watchdog interface
+            if(s[0] == "reg_wdi"):                              
+                self.add_port("pout_wdi", "OUT",  "STD_LOGIC", "\'1\'") 
+                
+            self.add_port(s[0] + "_mosi",     "OUT", "t_mem_mosi")      
+            self.add_port(s[0] + "_miso",     "IN", "t_mem_miso", "c_mem_miso_rst") 
+            
+        print self.make_instantiation_string()