Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
c9ce0dcf
Commit
c9ce0dcf
authored
10 years ago
by
Daniel van der Schuur
Browse files
Options
Downloads
Patches
Plain Diff
-Fixed component declaration.
parent
a59ca426
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+2
-126
2 additions, 126 deletions
...ications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
with
2 additions
and
126 deletions
applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+
2
−
126
View file @
c9ce0dcf
...
@@ -109,52 +109,29 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
...
@@ -109,52 +109,29 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
COMPONENT
qsys_unb1_correlator
is
COMPONENT
qsys_unb1_correlator
is
PORT
(
PORT
(
coe_ram_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_ram_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_reg_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_reg_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_mmdp_ctrl
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
mm_clk
:
out
std_logic
;
-- clk
mm_clk
:
out
std_logic
;
-- clk
coe_address_export_from_the_pio_system_info
:
out
std_logic_vector
(
4
downto
0
);
-- export
coe_address_export_from_the_pio_system_info
:
out
std_logic_vector
(
4
downto
0
);
-- export
coe_address_export_from_the_pio_pps
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_address_export_from_the_pio_pps
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_waitrequest_export_to_the_reg_tr_10GbE
:
in
std_logic
:
=
'X'
;
-- export
coe_reset_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_reset_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_epcs
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_pio_pps
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_pio_pps
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_writedata_export_from_the_pio_system_info
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_pio_system_info
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_write_export_from_the_reg_tr_xaui
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_tse_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_tse_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_tr_xaui
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_reset_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_dpmm_data
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_writedata_export_from_the_reg_mmdp_ctrl
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_address_export_from_the_reg_dpmm_ctrl
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_clk_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_clk_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_remu
:
out
std_logic
;
-- export
coe_read_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_read_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_write_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_write_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_dpmm_data
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_unb_sens
:
out
std_logic
;
-- export
coe_reg_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_reg_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_address_export_from_the_reg_tr_xaui
:
out
std_logic_vector
(
10
downto
0
);
-- export
coe_readdata_export_to_the_reg_dpmm_ctrl
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_reset_export_from_the_reg_mmdp_data
:
out
std_logic
;
-- export
coe_read_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_read_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_reg_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_reg_write_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_mmdp_data
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_read_export_from_the_reg_epcs
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_remu
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_reg_unb_sens
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_reg_unb_sens
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_ram_address_export_from_the_avs_eth_0
:
out
std_logic_vector
(
9
downto
0
);
-- export
coe_ram_address_export_from_the_avs_eth_0
:
out
std_logic_vector
(
9
downto
0
);
-- export
coe_waitrequest_export_to_the_reg_tr_xaui
:
in
std_logic
:
=
'X'
;
-- export
coe_clk_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_clk_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_readdata_export_to_the_pio_system_info
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_pio_system_info
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_write_export_from_the_reg_tr_10GbE
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_tr_xaui
:
out
std_logic
;
-- export
coe_writedata_export_from_the_rom_system_info
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_rom_system_info
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_address_export_from_the_reg_dpmm_data
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_address_export_from_the_reg_tr_10GbE
:
out
std_logic_vector
(
14
downto
0
);
-- export
coe_write_export_from_the_reg_mmdp_ctrl
:
out
std_logic
;
-- export
coe_reset_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_reset_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_address_export_from_the_reg_wdi
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_address_export_from_the_reg_wdi
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_write_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_write_export_from_the_pio_system_info
:
out
std_logic
;
-- export
...
@@ -164,139 +141,38 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
...
@@ -164,139 +141,38 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
coe_irq_export_to_the_avs_eth_0
:
in
std_logic
:
=
'X'
;
-- export
coe_irq_export_to_the_avs_eth_0
:
in
std_logic
:
=
'X'
;
-- export
phasedone_from_the_altpll_0
:
out
std_logic
;
-- export
phasedone_from_the_altpll_0
:
out
std_logic
;
-- export
coe_read_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_read_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_epcs
:
out
std_logic
;
-- export
reset_n
:
in
std_logic
:
=
'X'
;
-- reset_n
reset_n
:
in
std_logic
:
=
'X'
;
-- reset_n
coe_tse_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_tse_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_clk_export_from_the_reg_mmdp_ctrl
:
out
std_logic
;
-- export
coe_ram_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_ram_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_tse_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_tse_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
clk_0
:
in
std_logic
:
=
'X'
;
-- clk
clk_0
:
in
std_logic
:
=
'X'
;
-- clk
coe_read_export_from_the_reg_dpmm_ctrl
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_tr_xaui
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_writedata_export_from_the_reg_remu
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_write_export_from_the_reg_dpmm_data
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_unb_sens
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_reg_unb_sens
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_reg_tr_10GbE
:
out
std_logic_vector
(
31
downto
0
);
-- export
tse_clk
:
out
std_logic
;
-- clk
tse_clk
:
out
std_logic
;
-- clk
dp_clk
:
out
std_logic
;
-- clk
coe_reg_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_reg_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
epcs_clk
:
out
std_logic
;
-- clk
epcs_clk
:
out
std_logic
;
-- clk
coe_read_export_from_the_reg_tr_10GbE
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_tr_10GbE
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_dpmm_ctrl
:
out
std_logic
;
-- export
coe_tse_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_tse_read_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
out_port_from_the_pio_debug_wave
:
out
std_logic_vector
(
31
downto
0
);
-- export
out_port_from_the_pio_debug_wave
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_reg_dpmm_data
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_read_export_from_the_reg_tr_xaui
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_wdi
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_reg_wdi
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_reset_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_reset_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_read_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_read_export_from_the_pio_system_info
:
out
std_logic
;
-- export
cal_reconf_clk
:
out
std_logic
;
-- clk
coe_clk_export_from_the_reg_mmdp_data
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_epcs
:
out
std_logic
;
-- export
coe_write_export_from_the_reg_remu
:
out
std_logic
;
-- export
coe_ram_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_ram_readdata_export_to_the_avs_eth_0
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_read_export_from_the_reg_mmdp_data
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_epcs
:
out
std_logic_vector
(
31
downto
0
);
-- export
out_port_from_the_pio_wdi
:
out
std_logic
;
-- export
out_port_from_the_pio_wdi
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_dpmm_data
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_remu
:
out
std_logic
;
-- export
coe_read_export_from_the_reg_mmdp_ctrl
:
out
std_logic
;
-- export
coe_clk_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_clk_export_from_the_avs_eth_0
:
out
std_logic
;
-- export
coe_address_export_from_the_reg_mmdp_ctrl
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_write_export_from_the_reg_epcs
:
out
std_logic
;
-- export
coe_readdata_export_to_the_rom_system_info
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_rom_system_info
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_reset_export_from_the_reg_mmdp_ctrl
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_mmdp_data
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_write_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_write_export_from_the_reg_wdi
:
out
std_logic
;
-- export
coe_clk_export_from_the_reg_tr_xaui
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_wdi
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_readdata_export_to_the_reg_wdi
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_read_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_read_export_from_the_pio_pps
:
out
std_logic
;
-- export
coe_clk_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_clk_export_from_the_pio_system_info
:
out
std_logic
;
-- export
coe_writedata_export_from_the_pio_pps
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_writedata_export_from_the_pio_pps
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_address_export_from_the_reg_epcs
:
out
std_logic_vector
(
2
downto
0
);
-- export
coe_read_export_from_the_reg_dpmm_data
:
out
std_logic
;
-- export
coe_reset_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_reset_export_from_the_rom_system_info
:
out
std_logic
;
-- export
coe_writedata_export_from_the_reg_dpmm_ctrl
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_tse_waitrequest_export_to_the_avs_eth_0
:
in
std_logic
:
=
'X'
;
-- export
coe_tse_waitrequest_export_to_the_avs_eth_0
:
in
std_logic
:
=
'X'
;
-- export
coe_address_export_from_the_reg_mmdp_data
:
out
std_logic
;
--_vector(0 downto 0); -- export
coe_address_export_from_the_reg_unb_sens
:
out
std_logic_vector
(
2
downto
0
);
-- export
coe_address_export_from_the_reg_unb_sens
:
out
std_logic_vector
(
2
downto
0
);
-- export
coe_address_export_from_the_rom_system_info
:
out
std_logic_vector
(
9
downto
0
);
-- export
coe_address_export_from_the_rom_system_info
:
out
std_logic_vector
(
9
downto
0
);
-- export
coe_clk_export_from_the_reg_dpmm_ctrl
:
out
std_logic
;
-- export
coe_reg_address_export_from_the_avs_eth_0
:
out
std_logic_vector
(
3
downto
0
);
-- export
coe_reg_address_export_from_the_avs_eth_0
:
out
std_logic_vector
(
3
downto
0
);
-- export
coe_write_export_from_the_reg_mmdp_data
:
out
std_logic
;
-- export
coe_address_export_from_the_reg_remu
:
out
std_logic_vector
(
2
downto
0
);
-- export
areset_to_the_altpll_0
:
in
std_logic
:
=
'X'
;
-- export
areset_to_the_altpll_0
:
in
std_logic
:
=
'X'
;
-- export
locked_from_the_altpll_0
:
out
std_logic
;
-- export
locked_from_the_altpll_0
:
out
std_logic
;
-- export
coe_readdata_export_to_the_reg_tr_10GbE
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
coe_ram_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
)
-- export
coe_write_export_from_the_reg_dpmm_ctrl
:
out
std_logic
;
-- export
coe_reset_export_from_the_reg_tr_10GbE
:
out
std_logic
;
-- export
coe_ram_writedata_export_from_the_avs_eth_0
:
out
std_logic_vector
(
31
downto
0
);
-- export
coe_read_export_from_the_reg_remu
:
out
std_logic
;
-- export
reg_bsn_monitor_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_bsn_monitor_read_export
:
out
std_logic
;
-- export
reg_bsn_monitor_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_bsn_monitor_write_export
:
out
std_logic
;
-- export
reg_bsn_monitor_address_export
:
out
std_logic_vector
(
5
downto
0
);
-- export
reg_bsn_monitor_clk_export
:
out
std_logic
;
-- export
reg_bsn_monitor_reset_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_dp_offload_tx_read_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_dp_offload_tx_write_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_address_export
:
out
std_logic_vector
(
2
downto
0
);
-- export
reg_dp_offload_tx_clk_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_reset_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_dat_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_dp_offload_tx_hdr_dat_read_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_dat_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_dp_offload_tx_hdr_dat_write_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_dat_address_export
:
out
std_logic_vector
(
7
downto
0
);
-- export
reg_dp_offload_tx_hdr_dat_clk_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_dat_reset_export
:
out
std_logic
;
-- export
reg_dp_offload_rx_hdr_dat_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_dp_offload_rx_hdr_dat_read_export
:
out
std_logic
;
-- export
reg_dp_offload_rx_hdr_dat_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_dp_offload_rx_hdr_dat_write_export
:
out
std_logic
;
-- export
reg_dp_offload_rx_hdr_dat_address_export
:
out
std_logic_vector
(
7
downto
0
);
-- export
reg_dp_offload_rx_hdr_dat_clk_export
:
out
std_logic
;
-- export
reg_dp_offload_rx_hdr_dat_reset_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_ovr_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_dp_offload_tx_hdr_ovr_read_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_ovr_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_dp_offload_tx_hdr_ovr_write_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_ovr_address_export
:
out
std_logic_vector
(
6
downto
0
);
-- export
reg_dp_offload_tx_hdr_ovr_clk_export
:
out
std_logic
;
-- export
reg_dp_offload_tx_hdr_ovr_reset_export
:
out
std_logic
;
-- export
reg_diag_data_buffer_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_diag_data_buffer_read_export
:
out
std_logic
;
-- export
reg_diag_data_buffer_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_diag_data_buffer_write_export
:
out
std_logic
;
-- export
reg_diag_data_buffer_address_export
:
out
std_logic_vector
(
4
downto
0
);
-- export
reg_diag_data_buffer_clk_export
:
out
std_logic
;
-- export
reg_diag_data_buffer_reset_export
:
out
std_logic
;
-- export
ram_diag_data_buffer_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
ram_diag_data_buffer_read_export
:
out
std_logic
;
-- export
ram_diag_data_buffer_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
ram_diag_data_buffer_write_export
:
out
std_logic
;
-- export
ram_diag_data_buffer_address_export
:
out
std_logic_vector
(
13
downto
0
);
-- export
ram_diag_data_buffer_clk_export
:
out
std_logic
;
-- export
ram_diag_data_buffer_reset_export
:
out
std_logic
;
-- export
reg_diag_bg_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
reg_diag_bg_read_export
:
out
std_logic
;
-- export
reg_diag_bg_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
reg_diag_bg_write_export
:
out
std_logic
;
-- export
reg_diag_bg_address_export
:
out
std_logic_vector
(
2
downto
0
);
-- export
reg_diag_bg_clk_export
:
out
std_logic
;
-- export
reg_diag_bg_reset_export
:
out
std_logic
;
-- export
ram_diag_bg_readdata_export
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'X'
);
-- export
ram_diag_bg_read_export
:
out
std_logic
;
-- export
ram_diag_bg_writedata_export
:
out
std_logic_vector
(
31
downto
0
);
-- export
ram_diag_bg_write_export
:
out
std_logic
;
-- export
ram_diag_bg_address_export
:
out
std_logic_vector
(
11
downto
0
);
-- export
ram_diag_bg_clk_export
:
out
std_logic
;
-- export
ram_diag_bg_reset_export
:
out
std_logic
-- export
);
);
end
component
qsys_unb1_correlator
;
end
component
qsys_unb1_correlator
;
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment