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Commit c9b68415 authored by Pieter Donker's avatar Pieter Donker
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changed st.peripheral.yaml

parent 55374e30
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Pipeline #23422 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+ 13
− 2
View file @ c9b68415
...@@ -81,7 +81,16 @@ number_of_columns = 13 ...@@ -81,7 +81,16 @@ number_of_columns = 13
- - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - - - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - - PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
- - - - reset 0x0001e000 1 RW uint32 b[31:31] - - - - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256 JESD204B 1 12 REG rx_lane_ctrl_common 0x00020000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00020001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00020002 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_2 0x00020003 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_3 0x00020004 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_4 0x00020005 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_5 0x00020006 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_6 0x00020007 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_7 0x00020008 1 RW uint32 b[2:0] - - -
- - - - rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - - - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - - - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - - - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
...@@ -142,7 +151,7 @@ number_of_columns = 13 ...@@ -142,7 +151,7 @@ number_of_columns = 13
- - - - - 0x00032003 - - - b[31:0] b[63:32] - - - - - - - 0x00032003 - - - b[31:0] b[63:32] - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2 REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - - - - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024 RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[31:0] b[15:0] - 1024
REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - - REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024 RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024
...@@ -210,6 +219,8 @@ number_of_columns = 13 ...@@ -210,6 +219,8 @@ number_of_columns = 13
- - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - - - - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00060000 1008 RW cint64_ir b[31:0] b[31:0] - 4096 RAM_ST_XSQ 1 9 RAM data 0x00060000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00060001 - - - b[31:0] b[63:32] - - - - - - - 0x00060001 - - - b[31:0] b[63:32] - -
- - - - - 0x00060002 - - - b[31:0] b[95:64] - -
- - - - - 0x00060003 - - - b[31:0] b[127:96] - -
REG_CROSSLETS_INFO 1 1 REG offset 0x00070000 15 RW uint32 b[31:0] - - - REG_CROSSLETS_INFO 1 1 REG offset 0x00070000 15 RW uint32 b[31:0] - - -
- - - - step 0x0007000f 1 RW uint32 b[31:0] - - - - - - - step 0x0007000f 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00072000 1 RW uint32 b[31:0] - - - REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00072000 1 RW uint32 b[31:0] - - -
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+ 13
− 2
View file @ c9b68415
...@@ -81,7 +81,16 @@ number_of_columns = 13 ...@@ -81,7 +81,16 @@ number_of_columns = 13
- - - - station_id 0x0003b02b 1 RW uint32 b[15:0] - - - - - - - station_id 0x0003b02b 1 RW uint32 b[15:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x0003b074 1 RW uint32 b[30:0] - - - PIO_JESD_CTRL 1 1 REG enable 0x0003b074 1 RW uint32 b[30:0] - - -
- - - - reset 0x0003b074 1 RW uint32 b[31:31] - - - - - - - reset 0x0003b074 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x0003a014 1 RW uint32 b[16:0] - - 256 JESD204B 1 12 REG rx_lane_ctrl_common 0x0003a000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x0003a001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x0003a002 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_2 0x0003a003 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_3 0x0003a004 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_4 0x0003a005 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_5 0x0003a006 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_6 0x0003a007 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_7 0x0003a008 1 RW uint32 b[2:0] - - -
- - - - rx_dll_ctrl 0x0003a014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x0003a015 1 RW uint32 b[24:0] - - - - - - - rx_syncn_sysref_ctrl 0x0003a015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x0003a015 1 RW uint32 b[1:1] - - - - - - - rx_csr_sysref_always_on 0x0003a015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x0003a015 1 RW uint32 b[10:3] - - - - - - - rx_csr_rbd_offset 0x0003a015 1 RW uint32 b[10:3] - - -
...@@ -142,7 +151,7 @@ number_of_columns = 13 ...@@ -142,7 +151,7 @@ number_of_columns = 13
- - - - - 0x00000d43 - - - b[31:0] b[63:32] - - - - - - - 0x00000d43 - - - b[31:0] b[63:32] - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2 REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - - - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024 RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
REG_SI 1 1 REG enable 0x0003b07c 1 RW uint32 b[0:0] - - - REG_SI 1 1 REG enable 0x0003b07c 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00030000 1024 RW uint32 b[15:0] - - 1024 RAM_FIL_COEFS 1 16 RAM data 0x00030000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00038000 1024 RW cint16_ir b[31:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00038000 1024 RW cint16_ir b[31:0] - - 1024
...@@ -210,6 +219,8 @@ number_of_columns = 13 ...@@ -210,6 +219,8 @@ number_of_columns = 13
- - - - block_size 0x0003b00b 1 RO uint32 b[31:0] - - - - - - - block_size 0x0003b00b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096 RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - - - - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
REG_CROSSLETS_INFO 1 1 REG offset 0x0003b010 15 RW uint32 b[31:0] - - - REG_CROSSLETS_INFO 1 1 REG offset 0x0003b010 15 RW uint32 b[31:0] - - -
- - - - step 0x0003b01f 1 RW uint32 b[31:0] - - - - - - - step 0x0003b01f 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00000c02 1 RW uint32 b[31:0] - - - REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00000c02 1 RW uint32 b[31:0] - - -
......
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