Map g_pulse_phase = phs natural range to equivalent integer range of...

Map g_pulse_phase = phs natural range to equivalent integer range of c_pulse_init that is used by g_init of common_counter to avoid truncation warning for conversion to slv.

libraries/base/common/src/vhdl/common_pulser.vhd

@@ -38,7 +38,7 @@ USE common_lib.common_pkg.ALL;
 ENTITY common_pulser IS
   GENERIC (
     g_pulse_period : NATURAL := 25000;  -- nof clk cycles to get pulse period
-    g_pulse_phase  : INTEGER := 0
+    g_pulse_phase  : NATURAL := 0
   );
   PORT (
     rst            : IN  STD_LOGIC;
@@ -56,6 +56,12 @@ ARCHITECTURE rtl OF common_pulser IS
 
   CONSTANT c_pulse_period_w  : NATURAL := ceil_log2(g_pulse_period+1);
   
+  -- Map g_pulse_phase = phs natural range to equivalent integer range of c_pulse_init that is used by g_init of common_counter to avoid truncation warning for conversion to slv
+  -- For example for c_pulse_period_w = w = 3:
+  --  0 1 2 3  4  5  6  7
+  --  0 1 2 3 -4 -3 -2 -1  --> if p < 2**(w-1) then return phs else return phs-2**w
+  CONSTANT c_pulse_init      : INTEGER := sel_a_b(g_pulse_phase<2**(c_pulse_period_w-1), g_pulse_phase, g_pulse_phase-2**c_pulse_period_w);
+  
   SIGNAL cnt           : STD_LOGIC_VECTOR(c_pulse_period_w-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL cnt_en        : STD_LOGIC;
   SIGNAL cnt_clr       : STD_LOGIC;
@@ -82,7 +88,7 @@ BEGIN
   
   u_cnt : ENTITY common_lib.common_counter
   GENERIC MAP (
-    g_init      => g_pulse_phase,
+    g_init      => c_pulse_init,
     g_width     => c_pulse_period_w
   )
   PORT MAP (