Specified the fifo filee size of RX fifo

boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd

@@ -107,7 +107,7 @@ ARCHITECTURE str OF unb1_terminal_bg_mesh_db IS
   CONSTANT c_use_rx                  : BOOLEAN := TRUE;
   CONSTANT c_rx_output_use_fifo      : BOOLEAN := TRUE;   -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
   CONSTANT c_rx_output_fifo_size     : NATURAL := c_bram_m9k_fifo_depth;   -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
-  CONSTANT c_rx_output_fifo_fill     : NATURAL := 0;
+  CONSTANT c_rx_output_fifo_fill     : NATURAL := 128;
   CONSTANT c_rx_timeout_w            : NATURAL := 0;      -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
   CONSTANT c_mon_select              : NATURAL := 0;      
   CONSTANT c_mon_nof_words           : NATURAL := 1024;
@@ -230,7 +230,6 @@ BEGIN
     g_aux             => c_unb1_board_aux,
     g_dp_clk_use_pll  => TRUE,
     g_xo_clk_use_pll  => TRUE
-    
   )
   PORT MAP (
     -- Clock and reset signals