Copied from ip_arria10_e2sg/ddio/ and changed the technology_name to ip_agi027_xxxx.

libraries/technology/ip_agi027_xxxx/ddio/hdllib.cfg

+hdl_lib_name = ip_agi027_xxxx_ddio
+hdl_library_clause_name = ip_agi027_xxxx_ddio_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_ddio_in.vhd
+    ip_agi027_xxxx_ddio_out.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $HDL_WORK/libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_in_1/ip_agi027_xxxx_ddio_in_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_out_1/ip_agi027_xxxx_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_agi027_xxxx_ddio_in_1.ip
+    ip_agi027_xxxx_ddio_out_1.ip