Fit one packet in FIFO.

libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd

@@ -65,8 +65,13 @@ END dp_block_from_mm_dc;
 
 ARCHITECTURE str OF dp_block_from_mm_dc IS 
 
-  CONSTANT c_packet_size  : NATURAL := g_nof_data * g_data_size;  -- 512 * 2 = 1024 words.
-  CONSTANT c_fifo_size    : NATURAL := c_packet_size * 2;
+  CONSTANT c_packet_size  : NATURAL := g_nof_data * g_data_size;
+
+  -- Fit one packet in FIFO, and less than two, to avoid filling the FIFO with
+  -- multiple packets in case writing FIFO (mm_clk) is faster than reading
+  -- FIFO (dp_clk).
+  CONSTANT c_fifo_fill    : NATURAL := c_packet_size;
+  CONSTANT c_fifo_size    : NATURAL := c_packet_size + c_packet_size/2;
   CONSTANT c_start_addr_w : NATURAL := c_natural_w;
   CONSTANT c_delay_len    : NATURAL := c_meta_delay_len;
 
@@ -152,7 +157,7 @@ BEGIN
     g_bsn_w          => g_bsn_w,
     g_use_bsn        => TRUE,
     g_use_sync       => TRUE,
-    g_fifo_fill      => c_packet_size,
+    g_fifo_fill      => c_fifo_fill,
     g_fifo_size      => c_fifo_size
   )
   PORT MAP (