Add AVS_ETH_1_TSE. Rename AVS_ETH_0_MMS_REG into AVS_ETH_0_REG.

boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd

@@ -344,11 +344,17 @@ BEGIN
                                                            PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
                                                            
     -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-    u_mm_file_reg_eth0            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+    -- . 1GbE_I with TSE setup by NiosII
+    u_mm_file_reg_eth0_tse        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
+                                               PORT MAP(mm_rst, mm_clk, eth1g_eth0_tse_mosi, eth1g_eth0_tse_miso);
+    u_mm_file_reg_eth0_reg        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
                                                PORT MAP(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
-    u_mm_file_reg_eth1            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-    
+    u_mm_file_reg_eth0_ram        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
+                                               PORT MAP(mm_rst, mm_clk, eth1g_eth0_ram_mosi, eth1g_eth0_ram_miso);
+    -- . 1GbE_II with TSE setup in VHDL
+    u_mm_file_reg_eth1_tse        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
+                                               PORT MAP(mm_rst, mm_clk, eth1g_eth1_tse_mosi, eth1g_eth1_tse_miso);
+
     u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
                                                   PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
     u_mm_file_reg_tr_10GbE_back0     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")