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Commit c65245de authored by Eric Kooistra's avatar Eric Kooistra
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Rename clk_2x into clk_312 and similar clk_156.

parent 626cb5b6
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libraries/technology/mac_10g/tb_tech_mac_10g.vhd
+ 34
− 34
View file @ c65245de
...@@ -58,7 +58,7 @@ END tb_tech_mac_10g; ...@@ -58,7 +58,7 @@ END tb_tech_mac_10g;
ARCHITECTURE tb OF tb_tech_mac_10g IS ARCHITECTURE tb OF tb_tech_mac_10g IS
CONSTANT mm_clk_period : TIME := 20 ns; -- 50 MHz CONSTANT mm_clk_period : TIME := 20 ns; -- 50 MHz
CONSTANT tx_ref_clk_period : TIME := 6.4 ns; -- 156.25 MHz CONSTANT tx_ref_clk_156_period : TIME := 6.4 ns; -- 156.25 MHz
CONSTANT phy_delay : TIME := 0 ns; CONSTANT phy_delay : TIME := 0 ns;
CONSTANT c_st_loopback : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT CONSTANT c_st_loopback : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
...@@ -86,12 +86,12 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS ...@@ -86,12 +86,12 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
SIGNAL tx_ref_clk_2x : STD_LOGIC := '1'; -- mac_10g SIGNAL tx_ref_clk_312 : STD_LOGIC := '1'; -- mac_10g
SIGNAL tx_ref_clk : STD_LOGIC := '0'; -- mac_10g reference clock SIGNAL tx_ref_clk_156 : STD_LOGIC := '0'; -- mac_10g reference clock
SIGNAL tx_rst : STD_LOGIC; -- reset synchronous with tx_ref_clk SIGNAL tx_rst : STD_LOGIC; -- reset synchronous with tx_ref_clk_156
SIGNAL rx_phy_clk_2x : STD_LOGIC := '1'; -- mac_10g SIGNAL rx_phy_clk_312 : STD_LOGIC := '1'; -- mac_10g
SIGNAL rx_phy_clk : STD_LOGIC := '0'; -- mac_10g rx clock from phy = tx_ref_clk in this tb SIGNAL rx_phy_clk_156 : STD_LOGIC := '0'; -- mac_10g rx clock from phy = tx_ref_clk_156 in this tb
SIGNAL rx_rst : STD_LOGIC; -- reset synchronous with rx_phy_clk = tx_ref_clk in this tb SIGNAL rx_rst : STD_LOGIC; -- reset synchronous with rx_phy_clk_156 = tx_ref_clk_156 in this tb
-- 10G MAC control interface -- 10G MAC control interface
SIGNAL mm_init : STD_LOGIC := '1'; SIGNAL mm_init : STD_LOGIC := '1';
...@@ -128,14 +128,14 @@ BEGIN ...@@ -128,14 +128,14 @@ BEGIN
-- run 50 us -- run 50 us
mm_clk <= NOT mm_clk AFTER mm_clk_period/2; -- MM clock mm_clk <= NOT mm_clk AFTER mm_clk_period/2; -- MM clock
tx_ref_clk <= NOT tx_ref_clk AFTER tx_ref_clk_period/2; -- mac_10g tx reference clock tx_ref_clk_156 <= NOT tx_ref_clk_156 AFTER tx_ref_clk_156_period/2; -- mac_10g tx reference clock
tx_ref_clk_2x <= NOT tx_ref_clk_2x AFTER tx_ref_clk_period/4; tx_ref_clk_312 <= NOT tx_ref_clk_312 AFTER tx_ref_clk_156_period/4;
rx_phy_clk <= tx_ref_clk; -- use tx_ref_clk to model PHY rx_phy_clk_156 <= tx_ref_clk_156; -- use tx_ref_clk_156 to model PHY
rx_phy_clk_2x <= tx_ref_clk_2x; rx_phy_clk_312 <= tx_ref_clk_312;
mm_rst <= '1', '0' AFTER mm_clk_period*10; mm_rst <= '1', '0' AFTER mm_clk_period*10;
tx_rst <= '1', '0' AFTER tx_ref_clk_period*10; tx_rst <= '1', '0' AFTER tx_ref_clk_156_period*10;
rx_rst <= '1', '0' AFTER tx_ref_clk_period*10; rx_rst <= '1', '0' AFTER tx_ref_clk_156_period*10;
-- debug signals to ease monitoring in wave window -- debug signals to ease monitoring in wave window
tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0); tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
...@@ -172,9 +172,9 @@ BEGIN ...@@ -172,9 +172,9 @@ BEGIN
tx_sosi <= c_dp_sosi_rst; tx_sosi <= c_dp_sosi_rst;
WHILE mm_init/='0' LOOP WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(tx_ref_clk); WAIT UNTIL rising_edge(tx_ref_clk_156);
END LOOP; END LOOP;
proc_common_wait_some_cycles(tx_ref_clk, 10); proc_common_wait_some_cycles(tx_ref_clk_156, 10);
-- Loopback txp->rxp so use promiscuous mode or use DST_MAC = c_src_mac to send to itself -- Loopback txp->rxp so use promiscuous mode or use DST_MAC = c_src_mac to send to itself
...@@ -184,12 +184,12 @@ BEGIN ...@@ -184,12 +184,12 @@ BEGIN
-- . For I>46 the payload length is I and empty = 4 - (I mod 4) -- . For I>46 the payload length is I and empty = 4 - (I mod 4)
FOR I IN 0 TO c_nof_pkt-1 LOOP FOR I IN 0 TO c_nof_pkt-1 LOOP
proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_ref_clk, tx_en, tx_siso, tx_sosi); proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_ref_clk_156, tx_en, tx_siso, tx_sosi);
proc_common_wait_some_cycles(tx_ref_clk, 0); proc_common_wait_some_cycles(tx_ref_clk_156, 0);
END LOOP; END LOOP;
proc_common_wait_some_cycles(tx_ref_clk, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat); proc_common_wait_some_cycles(tx_ref_clk_156, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
proc_common_wait_some_cycles(tx_ref_clk, 100); proc_common_wait_some_cycles(tx_ref_clk_156, 100);
tb_end <= '1'; tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
...@@ -201,22 +201,22 @@ BEGIN ...@@ -201,22 +201,22 @@ BEGIN
rx_siso <= c_dp_siso_hold; rx_siso <= c_dp_siso_hold;
WHILE mm_init/='0' LOOP WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(rx_phy_clk); WAIT UNTIL rising_edge(rx_phy_clk_156);
END LOOP; END LOOP;
-- Receive forever -- Receive forever
WHILE TRUE LOOP WHILE TRUE LOOP
proc_tech_mac_10g_rx_packet(total_header, g_data_type, rx_phy_clk, rx_sosi, rx_siso); proc_tech_mac_10g_rx_packet(total_header, g_data_type, rx_phy_clk_156, rx_sosi, rx_siso);
END LOOP; END LOOP;
WAIT; WAIT;
END PROCESS; END PROCESS;
p_ff_store_tx_sosi_at_eop : PROCESS(tx_ref_clk) p_ff_store_tx_sosi_at_eop : PROCESS(tx_ref_clk_156)
VARIABLE vI : NATURAL := 0; VARIABLE vI : NATURAL := 0;
BEGIN BEGIN
IF rising_edge(tx_ref_clk) THEN IF rising_edge(tx_ref_clk_156) THEN
IF tx_sosi.eop='1' THEN IF tx_sosi.eop='1' THEN
expected_sosi_arr(vI) <= tx_sosi; expected_sosi_arr(vI) <= tx_sosi;
vI := vI +1; vI := vI +1;
...@@ -224,11 +224,11 @@ BEGIN ...@@ -224,11 +224,11 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
p_ff_verify_rx_sosi_at_eop : PROCESS(rx_phy_clk) p_ff_verify_rx_sosi_at_eop : PROCESS(rx_phy_clk_156)
VARIABLE vI : NATURAL := 0; VARIABLE vI : NATURAL := 0;
VARIABLE vLow : NATURAL := 0; VARIABLE vLow : NATURAL := 0;
BEGIN BEGIN
IF rising_edge(rx_phy_clk) THEN IF rising_edge(rx_phy_clk_156) THEN
IF rx_sosi.eop='1' THEN IF rx_sosi.eop='1' THEN
-- frame shorter than 64 get padded so em -- frame shorter than 64 get padded so em
IF c_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 THEN -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4 IF c_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 THEN -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4
...@@ -264,14 +264,14 @@ BEGIN ...@@ -264,14 +264,14 @@ BEGIN
csr_miso => mm_miso, csr_miso => mm_miso,
-- ST -- ST
tx_clk_2x => tx_ref_clk_2x, tx_clk_312 => tx_ref_clk_312,
tx_clk => tx_ref_clk, -- 156.25 MHz local reference tx_clk_156 => tx_ref_clk_156, -- 156.25 MHz local reference
tx_rst => tx_rst, tx_rst => tx_rst,
tx_snk_in => tx_sosi, -- 64 bit data tx_snk_in => tx_sosi, -- 64 bit data
tx_snk_out => tx_siso, tx_snk_out => tx_siso,
rx_clk_2x => rx_phy_clk_2x, rx_clk_312 => rx_phy_clk_312,
rx_clk => rx_phy_clk, -- 156.25 MHz from rx phy rx_clk_156 => rx_phy_clk_156, -- 156.25 MHz from rx phy
rx_rst => rx_rst, rx_rst => rx_rst,
rx_src_out => rx_sosi, -- 64 bit data rx_src_out => rx_sosi, -- 64 bit data
rx_src_in => rx_siso, rx_src_in => rx_siso,
...@@ -291,8 +291,8 @@ BEGIN ...@@ -291,8 +291,8 @@ BEGIN
xgmii_rx_data <= TRANSPORT xgmii_tx_data AFTER phy_delay; xgmii_rx_data <= TRANSPORT xgmii_tx_data AFTER phy_delay;
-- Verification -- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_ref_clk); tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_ref_clk_156);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_phy_clk); rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_phy_clk_156);
p_tb_end : PROCESS p_tb_end : PROCESS
BEGIN BEGIN
......
libraries/technology/mac_10g/tech_mac_10g.vhd
+ 13
− 13
View file @ c65245de
...@@ -80,14 +80,14 @@ ENTITY tech_mac_10g IS ...@@ -80,14 +80,14 @@ ENTITY tech_mac_10g IS
csr_miso : OUT t_mem_miso; csr_miso : OUT t_mem_miso;
-- ST -- ST
tx_clk_2x : IN STD_LOGIC := '0'; -- 312.5 MHz tx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
tx_clk : IN STD_LOGIC; -- 156.25 MHz local reference tx_clk_156 : IN STD_LOGIC; -- 156.25 MHz local reference
tx_rst : IN STD_LOGIC; tx_rst : IN STD_LOGIC;
tx_snk_in : IN t_dp_sosi; -- 64 bit data tx_snk_in : IN t_dp_sosi; -- 64 bit data
tx_snk_out : OUT t_dp_siso; tx_snk_out : OUT t_dp_siso;
rx_clk_2x : IN STD_LOGIC := '0'; -- 312.5 MHz rx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
rx_clk : IN STD_LOGIC; -- 156.25 MHz from rx phy rx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from rx phy
rx_rst : IN STD_LOGIC; rx_rst : IN STD_LOGIC;
rx_src_out : OUT t_dp_sosi; -- 64 bit data rx_src_out : OUT t_dp_sosi; -- 64 bit data
rx_src_in : IN t_dp_siso; rx_src_in : IN t_dp_siso;
...@@ -132,16 +132,16 @@ BEGIN ...@@ -132,16 +132,16 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_mac_10g_stratixiv u0 : ENTITY work.tech_mac_10g_stratixiv
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso, PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk, tx_rst, tx_mac_snk_in, tx_mac_snk_out, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk, rx_rst, rx_mac_src_out, rx_mac_src_in, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
xgmii_tx_data, xgmii_rx_data); xgmii_tx_data, xgmii_rx_data);
END GENERATE; END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ENTITY work.tech_mac_10g_arria10 u0 : ENTITY work.tech_mac_10g_arria10
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso, PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_2x, tx_clk, tx_rst, tx_mac_snk_in, tx_mac_snk_out, tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk_2x, rx_clk, rx_rst, rx_mac_src_out, rx_mac_src_in, rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
xgmii_tx_data, xgmii_rx_data); xgmii_tx_data, xgmii_rx_data);
END GENERATE; END GENERATE;
...@@ -168,7 +168,7 @@ BEGIN ...@@ -168,7 +168,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => tx_rst, rst => tx_rst,
clk => tx_clk, clk => tx_clk_156,
snk_out => tx_snk_out, snk_out => tx_snk_out,
snk_in => tx_snk_in, snk_in => tx_snk_in,
src_in => tx_remove_snk_out, src_in => tx_remove_snk_out,
...@@ -189,7 +189,7 @@ BEGIN ...@@ -189,7 +189,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => tx_rst, rst => tx_rst,
clk => tx_clk, clk => tx_clk_156,
snk_out => tx_remove_snk_out, snk_out => tx_remove_snk_out,
snk_in => tx_remove_snk_in, snk_in => tx_remove_snk_in,
src_in => tx_mac_snk_out, src_in => tx_mac_snk_out,
...@@ -208,7 +208,7 @@ BEGIN ...@@ -208,7 +208,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => rx_rst, rst => rx_rst,
clk => rx_clk, clk => rx_clk_156,
snk_out => rx_mac_src_in, snk_out => rx_mac_src_in,
snk_in => rx_mac_src_out, snk_in => rx_mac_src_out,
src_in => rx_mac_src_in_rl1, src_in => rx_mac_src_in_rl1,
...@@ -224,7 +224,7 @@ BEGIN ...@@ -224,7 +224,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => rx_rst, rst => rx_rst,
clk => rx_clk, clk => rx_clk_156,
usedw => fifo_usedw, usedw => fifo_usedw,
wr_ful => fifo_ful, wr_ful => fifo_ful,
rd_emp => fifo_emp, rd_emp => fifo_emp,
...@@ -242,7 +242,7 @@ BEGIN ...@@ -242,7 +242,7 @@ BEGIN
) )
PORT MAP ( PORT MAP (
rst => rx_rst, rst => rx_rst,
clk => rx_clk, clk => rx_clk_156,
snk_out => rx_fifo_src_in, snk_out => rx_fifo_src_in,
snk_in => rx_fifo_src_out, snk_in => rx_fifo_src_out,
src_in => rx_insert_src_in, src_in => rx_insert_src_in,
......
libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+ 8
− 8
View file @ c65245de
...@@ -41,14 +41,14 @@ ENTITY tech_mac_10g_arria10 IS ...@@ -41,14 +41,14 @@ ENTITY tech_mac_10g_arria10 IS
csr_miso : OUT t_mem_miso; csr_miso : OUT t_mem_miso;
-- ST -- ST
tx_clk_2x : IN STD_LOGIC; tx_clk_312 : IN STD_LOGIC;
tx_clk : IN STD_LOGIC; tx_clk_156 : IN STD_LOGIC;
tx_rst : IN STD_LOGIC; tx_rst : IN STD_LOGIC;
tx_snk_in : IN t_dp_sosi; tx_snk_in : IN t_dp_sosi;
tx_snk_out : OUT t_dp_siso; tx_snk_out : OUT t_dp_siso;
rx_clk_2x : IN STD_LOGIC; rx_clk_312 : IN STD_LOGIC;
rx_clk : IN STD_LOGIC; rx_clk_156 : IN STD_LOGIC;
rx_rst : IN STD_LOGIC; rx_rst : IN STD_LOGIC;
rx_src_out : OUT t_dp_sosi; rx_src_out : OUT t_dp_sosi;
rx_src_in : IN t_dp_siso; rx_src_in : IN t_dp_siso;
...@@ -98,8 +98,8 @@ BEGIN ...@@ -98,8 +98,8 @@ BEGIN
csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit
csr_waitrequest => csr_miso.waitrequest, csr_waitrequest => csr_miso.waitrequest,
tx_312_5_clk => tx_clk_2x, tx_312_5_clk => tx_clk_312,
tx_156_25_clk => tx_clk, tx_156_25_clk => tx_clk_156,
tx_rst_n => tx_rst_n, tx_rst_n => tx_rst_n,
avalon_st_tx_ready => tx_snk_out.ready, avalon_st_tx_ready => tx_snk_out.ready,
...@@ -117,8 +117,8 @@ BEGIN ...@@ -117,8 +117,8 @@ BEGIN
avalon_st_txstatus_data => OPEN, avalon_st_txstatus_data => OPEN,
avalon_st_txstatus_error => OPEN, avalon_st_txstatus_error => OPEN,
rx_312_5_clk => rx_clk_2x, rx_312_5_clk => rx_clk_312,
rx_156_25_clk => rx_clk, rx_156_25_clk => rx_clk_156,
rx_rst_n => rx_rst_n, rx_rst_n => rx_rst_n,
xgmii_rx => xgmii_rx_data, -- 72 bit xgmii_rx => xgmii_rx_data, -- 72 bit
......
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