Initial commit

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/apertif_unb1_correlator_filter.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+-- Purpose:
+
+ENTITY apertif_unb1_correlator_filter IS
+  GENERIC (
+    g_design_name             : STRING  := "apertif_unb1_correlator_filter";
+    g_design_note             : STRING  := "channel filter"; 
+    g_sim                     : BOOLEAN := FALSE; -- Overridden by TB
+    g_sim_level               : NATURAL := 0; 
+    g_sim_fast                : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
+    g_sim_unb_nr              : NATURAL := 0;
+    g_sim_node_nr             : NATURAL := 0;
+    g_stamp_date              : NATURAL := 0;    -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time              : NATURAL := 0;    -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn               : NATURAL := 0     -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK           : IN    STD_LOGIC; -- System Clock
+    PPS           : IN    STD_LOGIC; -- System Sync
+    WDI           : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA          : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB          : INOUT STD_LOGIC; -- FPGA interconnect line
+                  
+    -- Others     
+    VERSION       : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID            : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO        : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    sens_sc       : INOUT STD_LOGIC;
+    sens_sd       : INOUT STD_LOGIC;
+  
+    -- 1GbE Control Interface
+    ETH_clk       : IN    STD_LOGIC;
+    ETH_SGIN      : IN    STD_LOGIC;
+    ETH_SGOUT     : OUT   STD_LOGIC;
+
+    -- Transceiver clocks
+    SA_CLK        : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+    SB_CLK        : IN  STD_LOGIC; -- SerDes clock FN-BN (tr_mesh)
+
+    -- Mesh Serial I/O
+    FN_BN_0_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_0_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_1_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_1_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_2_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_2_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_3_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_3_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0)
+  );
+END apertif_unb1_correlator_filter;
+
+
+ARCHITECTURE str OF apertif_unb1_correlator_filter IS
+  
+BEGIN
+
+  u_revision : ENTITY work.apertif_unb1_correlator_nodes
+  GENERIC MAP (    
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,        
+    g_sim_level   => g_sim_level,
+    g_sim_fast    => g_sim_fast,               
+    g_sim_unb_nr  => g_sim_unb_nr, 
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date, 
+    g_stamp_time  => g_stamp_time, 
+    g_stamp_svn   => g_stamp_svn
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK           => CLK,           
+    PPS           => PPS,           
+    WDI           => WDI,           
+    INTA          => INTA,          
+    INTB          => INTB,          
+                                   
+    VERSION       => VERSION,       
+    ID            => ID,            
+    TESTIO        => TESTIO,
+                                   
+    sens_sc       => sens_sc,       
+    sens_sd       => sens_sd,       
+                                   
+    ETH_clk       => ETH_clk,       
+    ETH_SGIN      => ETH_SGIN,      
+    ETH_SGOUT     => ETH_SGOUT,     
+                                   
+    SA_CLK        => SA_CLK,        
+    SB_CLK        => SB_CLK,        
+                                   
+    FN_BN_0_TX    => FN_BN_0_TX,    
+    FN_BN_0_RX    => FN_BN_0_RX,    
+    FN_BN_1_TX    => FN_BN_1_TX,    
+    FN_BN_1_RX    => FN_BN_1_RX,    
+    FN_BN_2_TX    => FN_BN_2_TX,    
+    FN_BN_2_RX    => FN_BN_2_RX,    
+    FN_BN_3_TX    => FN_BN_3_TX,    
+    FN_BN_3_RX    => FN_BN_3_RX,    
+
+    SI_FN_0_TX    => OPEN,    
+    SI_FN_0_RX    => (OTHERS => '0'),    
+    SI_FN_1_TX    => OPEN,    
+    SI_FN_1_RX    => (OTHERS => '0'),    
+    SI_FN_2_TX    => OPEN,    
+    SI_FN_2_RX    => (OTHERS => '0'),    
+    SI_FN_3_TX    => OPEN,    
+    SI_FN_3_RX    => (OTHERS => '0'),    
+                                   
+    SI_FN_0_CNTRL => OPEN, 
+    SI_FN_1_CNTRL => OPEN, 
+    SI_FN_2_CNTRL => OPEN, 
+    SI_FN_3_CNTRL => OPEN, 
+    SI_FN_RSTN    => OPEN    
+  );
+END str;
+

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/apertif_unb1_correlator_filter_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg

+hdl_lib_name = apertif_unb1_correlator_filter
+hdl_library_clause_name = apertif_unb1_correlator_filter_lib
+hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus/qsys_apertif_unb1_correlator.qsys .
+    ../../src/hex/ hex
+
+modelsim_copy_files = 
+    ../../src/hex hex
+
+synth_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_filter/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
+    ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
+    ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
+    ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_input.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_mesh.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_processing.vhd
+    ../../src/vhdl/apertif_unb1_correlator_nodes.vhd
+    apertif_unb1_correlator_filter.vhd
+    
+test_bench_files = 
+    tb_apertif_unb1_correlator_filter.vhd
+
+quartus_qsf_files = 
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    apertif_unb1_correlator_filter_pins.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_filter/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.qip
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/tb_apertif_unb1_correlator_filter.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Description:
+-- Usage:
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_apertif_unb1_correlator_filter IS
+END tb_apertif_unb1_correlator_filter;
+
+ARCHITECTURE tb OF tb_apertif_unb1_correlator_filter IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 7; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_sa_clk_period   : TIME := 6.4 ns;  
+  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000; 
+
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+  SIGNAL sa_clk              : STD_LOGIC := '1';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+ 
+  SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_1_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_2_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_3_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_dut : ENTITY work.apertif_unb1_correlator_filter
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp,
+      
+      -- Transceiver clocks
+      SA_CLK      => sa_clk,  --  : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+      SB_CLK      => sa_clk,
+
+      FN_BN_0_RX  => fn_bn_0_tx,
+      FN_BN_0_TX  => fn_bn_0_tx,
+
+      FN_BN_1_RX  => fn_bn_1_tx,
+      FN_BN_1_tX  => fn_bn_1_tx,
+
+      FN_BN_2_RX  => fn_bn_2_tx,
+      FN_BN_2_TX  => fn_bn_2_tx,
+
+      FN_BN_3_RX  => fn_bn_3_tx, 
+      FN_BN_3_TX  => fn_bn_3_tx  
+    );
+
+END tb;

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/tc_apertif_unb1_correlator_filter.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the apertif_unb1_correlator_mesh_distr_ref design.
+
+   Description:
+
+    
+   Usage:
+
+   > python tc_apertif_unb1_correlator_mesh_distr_ref.py --gn 0:7 --sim 
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import unb_apertif as apr
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_bsn_monitor
+import pi_ppsh  
+import pi_st_sst  
+import dsp_test
+
+import sys, os
+import subprocess  
+import time
+import pylab as pl
+import numpy as np
+import scipy as sp
+import random
+from tools import *
+from common import *  
+import mem_init_file
+
+###############################################################################
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name                   Value   Default   Description
+# START_VHDL_GENERICS
+g_nof_input_streams = 12       # 16 
+g_blocks_per_sync   = 16 #32   # 781250
+
+# Define settings for the block generator
+c_bg_nof_streams          = g_nof_input_streams 
+c_bg_ram_size             = 128
+c_db_nof_streams          = g_nof_input_streams
+c_db_ram_size             = 8
+c_samples_per_packet      = 128
+c_gapsize                 = 64
+c_mem_low_addr            = 0
+c_mem_high_addr           = c_samples_per_packet-1
+c_bsn_init                = 42
+c_in_dat_w                = 8
+c_nof_read_back_samples   = 1
+c_nof_10GbE_streams       = 3
+c_nof_lanes               = 4      
+c_nof_regs_per_stat       = 2           # The number of registers used for one statistic value
+
+c_write_bg_data            = False 
+c_write_bg_data_to_file    = False  
+                             
+tc.append_log(3, '>>>')      
+tc.append_log(1, '>>> Title : Test script for apertif_unb1_correlator_mesh_distr_ref' )
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+tc.set_result('PASSED')
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create block generator instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, g_nof_input_streams, c_bg_ram_size, instanceName='INPUT')
+
+# Create databuffer instances
+db_proc = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'PROC', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+
+# Create bsn-monitor instance
+bsn = pi_bsn_monitor.PiBsnMonitor(tc, io, nofStreams=2)
+
+# - Create statistics instance                                                                                
+st = pi_st_sst.PiStSst(tc, io, g_nof_input_streams, c_samples_per_packet, c_nof_regs_per_stat)
+
+# Create dsp_test instance for helpful methods
+dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+pps = pi_ppsh.PiPpsh(tc, io, nodeNr=tc.nodeFnNrs)
+
+if __name__ == "__main__":  
+     
+    ################################################################################
+    ##
+    ## Initialize the blockgenerators
+    ##
+    ################################################################################
+    # - Write settings to the block generator 
+    tc.append_log(3, '>>>')
+    tc.append_log(3, '>>> Write settings to the block generator')
+    tc.append_log(3, '>>>')
+
+    bg.write_block_gen_settings(c_samples_per_packet, g_blocks_per_sync, c_gapsize, c_mem_low_addr, c_mem_high_addr, c_bsn_init)
+    
+    # - Create a list with the input data and write it to the RAMs of the block generator
+    tc.append_log(3, '>>>')
+    tc.append_log(3, '>>> Write data to the waveform RAM of all channels')
+    tc.append_log(3, '>>>')
+    inputData = []
+    
+    dataList=[]
+    for h in range(tc.nofNodes):
+        nodeData = []
+        for i in xrange(c_nof_10GbE_streams):   #3
+            for j in xrange(c_nof_lanes):       #4
+                data = []
+                for k in xrange(0, c_samples_per_packet):
+                    real = (c_nof_10GbE_streams*h + i) & (2**c_in_dat_w-1)   # Telescope-stream number [23:0] in real part. Used as source-identifier. 
+                    imag = (2*j+ (k % 2)) & (2**c_in_dat_w-1)                # Alternatng destination number in imag part: (0,1) (2,3) 4,5) (6,7)
+                    data.append((imag << c_in_dat_w) + real)   
+                nodeData.append(data)
+        dataList.append(nodeData)
+    for i in dataList:
+        print i
+    inputData = []
+    in_h = 0
+    for h in tc.nodeNrs:   
+        for i in xrange(g_nof_input_streams):
+            if c_write_bg_data == True:      
+                bg.write_waveform_ram(dataList[in_h][i], i, [h])
+            if c_write_bg_data_to_file == True:                                                                   
+                filename = "../../src/hex/node" + str(h) + "/bg_in_data_mesh_distr_" + str(i) + ".hex"
+                mem_init_file.list_to_hex(list_in=dataList[in_h][i], filename=filename, mem_width=c_nof_complex*c_in_dat_w, mem_depth=2**(ceil_log2(c_bg_ram_size)))
+            dataListComplex = bg.convert_concatenated_to_complex(dataList[in_h][i], c_in_dat_w)
+            inputData.append(dataListComplex)  
+        in_h = in_h+1
+    
+    # - Enable the block generator
+    tc.append_log(3, '>>>')
+    tc.append_log(3, '>>> Start the block generator')
+    tc.append_log(3, '>>>')
+    tc.append_log(3, '')
+    
+    bg.write_enable_pps()
+    
+#    bsn.read_bsn_monitor(0)
+#    bsn.read_bsn_monitor(1)
+   
+    do_until_ge(db_proc.read_nof_words, ms_retry=3000, val=c_db_ram_size, s_timeout=3600)
+    
+#    bsn.read_bsn_monitor(0)
+#    bsn.read_bsn_monitor(1)
+    
+    ###############################################################################
+    #
+    # Read data from data buffer
+    #
+    ###############################################################################
+    db_out = []
+    for i in range(c_bg_nof_streams): 
+        db_out.append(flatten(db_proc.read_data_buffer(streamNr=i, n=c_nof_read_back_samples, radix='uns', width=c_nof_complex*c_in_dat_w, nofColumns=8)))
+
+    ###############################################################################
+    #
+    # Verify data
+    #
+    ###############################################################################
+    tc.append_log(0, 'The Real output ')
+    for i in db_out: 
+        db_re = []  
+        for j in i:                        
+            real = j & 0xFF
+            db_re.append(real)
+        tc.append_log(0, '%s' % str(db_re)) 
+
+    tc.append_log(3, '')
+    tc.append_log(0, 'The Imaginary output ')
+    for i in db_out:                                             
+        db_im = []  
+        for j in i:                        
+            imag = (j & 0xFF00) >> c_in_dat_w
+            db_im.append(imag)
+        tc.append_log(0, '%s' % str(db_im))       
+        
+        
+#        tc.append_log(0, '%s' % str((i & 0xFF00) >> c_in_dat_w)) 
+
+#    bsn.read_bsn_monitor(0)
+#    bsn.read_bsn_monitor(1)
+
+
+  #  for i in range(c_bg_nof_streams): 
+  #      for j in range(tc.nofNodes): 
+  #          for k in range(c_nof_read_back_samples):    
+  #              if db_out_re[i][j*c_nof_read_back_samples + k] != i:
+  #                  tc.append_log(1, 'Error in real part. Expected %d. Received %d', (i,db_out_re[i][j*c_nof_read_back_samples + k]))      
+  #                  tc.set_result('FAILED')
+  #              if j < 4:
+  #                  if db_out_im[i][j*c_nof_read_back_samples + k] != j*2:
+  #                      tc.append_log(1, 'Error in imag part. Expected %d. Received %d', (j*2,db_out_im[i][j*c_nof_read_back_samples + k]))      
+  #                      tc.set_result('FAILED')
+  #              else:
+  #                  if db_out_im[i][j*c_nof_read_back_samples + k] != j*2+1:
+  #                      tc.append_log(1, 'Error in imag part. Expected %d. Received %d', (j*2+1,db_out_im[i][j*c_nof_read_back_samples + k]))          
+  #                      tc.set_result('FAILED')
+
+    ###############################################################################
+    # End
+    tc.set_section_id('')
+    tc.append_log(3, '')
+    tc.append_log(3, '>>>')
+    tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+    tc.append_log(3, '>>>')
+    
+    sys.exit(tc.get_result())
+
+
+