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Commit c4ae3d10 authored by Pepping's avatar Pepping
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Initial commit fringe_stop library

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hdl_lib_name = fringe_stop
hdl_library_clause_name = fringe_stop_lib
hdl_lib_uses_synth = common common_mult technology mm dp
hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
src/vhdl/fringe_stop_unit.vhd
test_bench_files =
tb/vhdl/tb_fringe_stop_unit.vhd
regression_test_vhdl =
# no self checking tb available yet
[modelsim_project_file]
[quartus_project_file]
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: The bf_unit implements a beamformer algorithm. The algorithm takes a
-- subband sample of all antenna inputs and then calculates all the beamlets
-- for these subband samples by feeding the multiplier with the according weight
-- factors. A set of ss_wide instantiations is used for data distribution over
-- the multipliers and is used to retreive the same subband sample multiple
-- times.
--
-- The bf_unit connects the memory with the weightfactors and the output of the
-- ss_wide selection unit to the complex multiplier. The output of the multiplier
-- is fed to a an adder tree for accumulation. After accumulation the data is
-- passed on to two quantizers in parallel. First quantizer is used to shape
-- the data for the beamlet statistics unit. Second quantizer is used to shape
-- the data for the "normal" output that can be passed on to for instance a correlator.
--
-- The weight-memories can be pre-initialized for simulation using .hex files. The
-- naming convention for these files is:
--
-- weights_x_y.hex
--
-- where "weights" is the generic g_bf_weights_file_name
-- "x" is the bf_unit number
-- "y" is the signal path numner.
--
-- RAM init files (.hex files) only work when g_weights_write_only is set to FALSE.
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY common_lib, common_mult_lib, technology_lib, dp_lib;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY fringe_stop_unit IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_fs_offset_w : NATURAL := 10; -- Width of the offset of the linear coefficient
g_fs_step_w : NATURAL := 17; -- Width of the step of the linear coefficient
g_nof_channels : NATURAL := 256 -- Number of serial channels for which the fringe stopping must be applied uniquely
);
PORT (
-- System
dp_rst : IN STD_LOGIC := '0';
dp_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
-- MM interface
ram_fringe_stop_offset_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_fringe_stop_offset_miso : OUT t_mem_miso := c_mem_miso_rst;
ram_fringe_stop_step_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_fringe_stop_step_miso : OUT t_mem_miso := c_mem_miso_rst;
-- ST interface
in_sosi : IN t_dp_sosi;
in_siso : OUT t_dp_siso;
out_sosi : OUT t_dp_sosi
);
END fringe_stop_unit;
ARCHITECTURE str OF fringe_stop_unit IS
CONSTANT c_fs_ram_w : POSITIVE := ceil_log2(g_nof_channels);
TYPE reg_type IS RECORD
in_sosi : t_dp_sosi;
END RECORD;
SIGNAL r, rin : reg_type;
SIGNAL fs_addr : STD_LOGIC_VECTOR(c_fs_ram_w-1 DOWNTO 0);
SIGNAL fs_offset_data : STD_LOGIC_VECTOR(g_fs_offset_w-1 DOWNTO 0);
SIGNAL fs_step_data : STD_LOGIC_VECTOR(g_fs_step_w-1 DOWNTO 0);
BEGIN
------------------------------------------------------------------------------
-- Input registers
------------------------------------------------------------------------------
comb : PROCESS(r, in_sosi)
VARIABLE v : reg_type;
BEGIN
v := r;
v.in_sosi := in_sosi;
rin <= v;
END PROCESS comb;
regs : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
r <= rin;
END IF;
END PROCESS;
------------------------------------------------------------------------------
-- Fringe stop Offset memory (dual page and dual port)
------------------------------------------------------------------------------
u_fringe_stop_offset_ram : ENTITY common_lib.common_paged_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_str => "use_adr",
g_data_w => g_fs_offset_w,
g_nof_pages => 2,
g_page_sz => g_nof_channels,
g_start_page_a => 0,
g_start_page_b => 1,
g_rd_latency => 1,
g_true_dual_port => TRUE
)
PORT MAP(
rst_a => mm_rst,
clk_a => mm_clk,
next_page_a => in_sosi.sync,
adr_a => ram_fringe_stop_offset_mosi.address(c_fs_ram_w-1 DOWNTO 0),
wr_en_a => ram_fringe_stop_offset_mosi.wr,
wr_dat_a => ram_fringe_stop_offset_mosi.data(g_fs_offset_w-1 DOWNTO 0),
rd_en_a => ram_fringe_stop_offset_mosi.rd,
rd_dat_a => ram_fringe_stop_offset_miso.data(g_fs_offset_w-1 DOWNTO 0),
rd_val_a => ram_fringe_stop_offset_miso.rdval,
rst_b => dp_rst,
clk_b => dp_clk,
next_page_b => in_sosi.sync,
adr_b => fs_addr,
wr_en_b => '0',
wr_dat_b => (OTHERS =>'0'),
rd_en_b => in_sosi.valid,
rd_dat_b => fs_offset_data,
rd_val_b => OPEN
);
------------------------------------------------------------------------------
-- Fringe stop Step memory (dual page and dual port)
------------------------------------------------------------------------------
u_fringe_stop_step_ram : ENTITY common_lib.common_paged_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_str => "use_adr",
g_data_w => g_fs_step_w,
g_nof_pages => 2,
g_page_sz => g_nof_channels,
g_start_page_a => 0,
g_start_page_b => 1,
g_rd_latency => 1,
g_true_dual_port => TRUE
)
PORT MAP(
rst_a => mm_rst,
clk_a => mm_clk,
next_page_a => in_sosi.sync,
adr_a => ram_fringe_stop_step_mosi.address(c_fs_ram_w-1 DOWNTO 0),
wr_en_a => ram_fringe_stop_step_mosi.wr,
wr_dat_a => ram_fringe_stop_step_mosi.data(g_fs_step_w-1 DOWNTO 0),
rd_en_a => ram_fringe_stop_step_mosi.rd,
rd_dat_a => ram_fringe_stop_step_miso.data(g_fs_step_w-1 DOWNTO 0),
rd_val_a => ram_fringe_stop_step_miso.rdval,
rst_b => dp_rst,
clk_b => dp_clk,
next_page_b => in_sosi.sync,
adr_b => fs_addr,
wr_en_b => '0',
wr_dat_b => (OTHERS =>'0'),
rd_en_b => in_sosi.valid,
rd_dat_b => fs_step_data,
rd_val_b => OPEN
);
------------------------------------------------------------------------------
-- Counter used to create addresses for both the offset ram and the step ram
------------------------------------------------------------------------------
fs_adrs_cnt : ENTITY common_lib.common_counter
GENERIC MAP(
g_latency => 1,
g_init => 0,
g_width => c_fs_ram_w,
g_max => g_nof_channels-1,
g_step_size => 1
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
cnt_clr => in_sosi.eop,
cnt_en => in_sosi.valid,
count => fs_addr
);
-- u_multiplier : ENTITY common_mult_lib.common_complex_mult
-- GENERIC MAP (
-- g_technology => g_technology,
-- g_variant => "IP",
-- g_in_a_w => g_bf.in_weight_w,
-- g_in_b_w => g_bf.in_dat_w,
-- g_out_p_w => c_prod_w,
-- g_conjugate_b => c_conjugate,
-- g_pipeline_input => 1,
-- g_pipeline_product => 0,
-- g_pipeline_adder => 1,
-- g_pipeline_output => 1
-- )
-- PORT MAP (
-- rst => dp_rst,
-- clk => dp_clk,
-- in_ar => weight_re_arr(I),
-- in_ai => weight_im_arr(I),
-- in_br => data_re_arr(I),
-- in_bi => data_im_arr(I),
-- out_pr => prod_re_arr(I),
-- out_pi => prod_im_arr(I)
-- );
--
END str;
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