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Commit c4a6e219 authored by Eric Kooistra's avatar Eric Kooistra
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Remove ip/ level and ip_arria10_tse_sgmii_gx_top.vhd wrapper.

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libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl → libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
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− 1
View file @ c4a6e219
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg # - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl # - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/ip/generated/sim" set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
#vlib ./work/ ;# Assume library work already exists #vlib ./work/ ;# Assume library work already exists
......
libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
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hdl_lib_name = ip_arria10_tse_sgmii_gx hdl_lib_name = ip_arria10_tse_sgmii_gx
hdl_library_clause_name = ip_arria10_tse_sgmii_gx_lib hdl_library_clause_name = ip_arria10_tse_sgmii_gx_altera_eth_tse_140
hdl_lib_uses = ip_arria10_tse_sgmii_gx_altera_eth_tse_140 common hdl_lib_uses = common
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR build_dir_synth = $HDL_BUILD_DIR
synth_files = synth_files =
ip_arria10_tse_sgmii_gx_top.vhd
test_bench_files = test_bench_files =
tb_ip_arria10_tse_sgmii_gx_top.vhd tb_ip_arria10_tse_sgmii_gx.vhd
modelsim_search_libraries = modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
......
libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx_top.vhd deleted 100644 → 0
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View file @ 617aad8a
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_tse_sgmii_gx.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_tse_sgmii_gx_altera_eth_tse_140 library
-- in the tech_tse library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_tse_sgmii_gx.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_tse_sgmii_gx_altera_eth_tse_140;
entity ip_arria10_tse_sgmii_gx_top is
port (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
reset : in std_logic := '0'; -- reset_connection.reset
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
reg_rd : in std_logic := '0'; -- .read
reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reg_wr : in std_logic := '0'; -- .write
reg_busy : out std_logic; -- .waitrequest
reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
ff_rx_eop : out std_logic; -- .endofpacket
rx_err : out std_logic_vector(5 downto 0); -- .error
ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
ff_rx_rdy : in std_logic := '0'; -- .ready
ff_rx_sop : out std_logic; -- .startofpacket
ff_rx_dval : out std_logic; -- .valid
ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
ff_tx_eop : in std_logic := '0'; -- .endofpacket
ff_tx_err : in std_logic := '0'; -- .error
ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
ff_tx_rdy : out std_logic; -- .ready
ff_tx_sop : in std_logic := '0'; -- .startofpacket
ff_tx_wren : in std_logic := '0'; -- .valid
ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
ff_tx_septy : out std_logic; -- .ff_tx_septy
tx_ff_uflow : out std_logic; -- .tx_ff_uflow
ff_tx_a_full : out std_logic; -- .ff_tx_a_full
ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
ff_rx_dsav : out std_logic; -- .ff_rx_dsav
ff_rx_a_full : out std_logic; -- .ff_rx_a_full
ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
led_crs : out std_logic; -- status_led_connection.crs
led_link : out std_logic; -- .link
led_col : out std_logic; -- .col
led_an : out std_logic; -- .an
led_char_err : out std_logic; -- .char_err
led_disp_err : out std_logic; -- .disp_err
rx_recovclkout : out std_logic; -- serdes_control_connection.export
ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
rxp : in std_logic := '0'; -- serial_connection.rxp
txp : out std_logic; -- .txp
tx_serial_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
rx_cdr_refclk : in std_logic := '0'; -- rx_cdr_refclk.clk
tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
end ip_arria10_tse_sgmii_gx_top;
architecture str of ip_arria10_tse_sgmii_gx_top is
begin
u_ip_arria10_tse_sgmii_gx : entity ip_arria10_tse_sgmii_gx_altera_eth_tse_140.ip_arria10_tse_sgmii_gx
port map (
clk => clk, -- control_port_clock_connection.clk
reset => reset, -- reset_connection.reset
reg_data_out => reg_data_out, -- control_port.readdata
reg_rd => reg_rd, -- .read
reg_data_in => reg_data_in, -- .writedata
reg_wr => reg_wr, -- .write
reg_busy => reg_busy, -- .waitrequest
reg_addr => reg_addr, -- .address
ff_rx_clk => ff_rx_clk, -- receive_clock_connection.clk
ff_tx_clk => ff_tx_clk, -- transmit_clock_connection.clk
ff_rx_data => ff_rx_data, -- receive.data
ff_rx_eop => ff_rx_eop, -- .endofpacket
rx_err => rx_err, -- .error
ff_rx_mod => ff_rx_mod, -- .empty
ff_rx_rdy => ff_rx_rdy, -- .ready
ff_rx_sop => ff_rx_sop, -- .startofpacket
ff_rx_dval => ff_rx_dval, -- .valid
ff_tx_data => ff_tx_data, -- transmit.data
ff_tx_eop => ff_tx_eop, -- .endofpacket
ff_tx_err => ff_tx_err, -- .error
ff_tx_mod => ff_tx_mod, -- .empty
ff_tx_rdy => ff_tx_rdy, -- .ready
ff_tx_sop => ff_tx_sop, -- .startofpacket
ff_tx_wren => ff_tx_wren, -- .valid
ff_tx_crc_fwd => ff_tx_crc_fwd, -- mac_misc_connection.ff_tx_crc_fwd
ff_tx_septy => ff_tx_septy, -- .ff_tx_septy
tx_ff_uflow => tx_ff_uflow, -- .tx_ff_uflow
ff_tx_a_full => ff_tx_a_full, -- .ff_tx_a_full
ff_tx_a_empty => ff_tx_a_empty, -- .ff_tx_a_empty
rx_err_stat => rx_err_stat, -- .rx_err_stat
rx_frm_type => rx_frm_type, -- .rx_frm_type
ff_rx_dsav => ff_rx_dsav, -- .ff_rx_dsav
ff_rx_a_full => ff_rx_a_full, -- .ff_rx_a_full
ff_rx_a_empty => ff_rx_a_empty, -- .ff_rx_a_empty
ref_clk => ref_clk, -- pcs_ref_clk_clock_connection.clk
led_crs => led_crs, -- status_led_connection.crs
led_link => led_link, -- .link
led_col => led_col, -- .col
led_an => led_an, -- .an
led_char_err => led_char_err, -- .char_err
led_disp_err => led_disp_err, -- .disp_err
rx_recovclkout => rx_recovclkout, -- serdes_control_connection.export
rxp => rxp, -- serial_connection.rxp
txp => txp, -- .txp
tx_serial_clk => tx_serial_clk, -- tx_serial_clk.clk
rx_cdr_refclk => rx_cdr_refclk, -- rx_cdr_refclk.clk
tx_analogreset => tx_analogreset, -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset, -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset, -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset, -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy, -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy, -- rx_cal_busy.rx_cal_busy
rx_set_locktodata => rx_set_locktodata, -- rx_set_locktodata.rx_set_locktodata
rx_set_locktoref => rx_set_locktoref, -- rx_set_locktoref.rx_set_locktoref
rx_is_lockedtoref => rx_is_lockedtoref, -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata -- rx_is_lockedtodata.rx_is_lockedtodata
);
end str;
libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx_top.vhd → libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
+ 5
− 5
View file @ c4a6e219
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Purpose: Testbench for ip_arria10_tse_sgmii_gx_top. -- Purpose: Testbench for ip_arria10_tse_sgmii_gx.
-- Description: -- Description:
-- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true -- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
-- at the tb_end. -- at the tb_end.
...@@ -33,11 +33,11 @@ USE IEEE.numeric_std.ALL; ...@@ -33,11 +33,11 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
ENTITY tb_ip_arria10_tse_sgmii_gx_top IS ENTITY tb_ip_arria10_tse_sgmii_gx IS
END tb_ip_arria10_tse_sgmii_gx_top; END tb_ip_arria10_tse_sgmii_gx;
ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_gx_top IS ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_gx IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
...@@ -632,7 +632,7 @@ BEGIN ...@@ -632,7 +632,7 @@ BEGIN
WAIT; WAIT;
END PROCESS; END PROCESS;
dut : ENTITY work.ip_arria10_tse_sgmii_gx_top dut : ENTITY work.ip_arria10_tse_sgmii_gx
-- The ip_arria10_tse_sgmii_gx needs to be regenerated if its parameters are changed. -- The ip_arria10_tse_sgmii_gx needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
......
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