corrected fifo size

libraries/io/eth/src/vhdl/eth_tester_rx.vhd

@@ -80,7 +80,7 @@ ARCHITECTURE str OF eth_tester_rx IS
   -- Rx FIFO size can be much less than rx_block_sz_max, because st_clk >
   -- eth_clk rate, but with st level tx-rx loopback the Rx FIFO does need
   -- rx_block_sz_max FIFO size.
-  CONSTANT rx_block_sz_max        : NATURAL := c_eth_tester_rx_block_len_max / c_in_data_w; 
+  CONSTANT rx_block_sz_max        : NATURAL := c_eth_tester_rx_block_len_max / g_nof_octet_input; 
   CONSTANT c_fifo_size            : NATURAL := true_log_pow2(rx_block_sz_max);
 
   SIGNAL rx_udp_data         : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);