Created files for beamlet reordering needed for ARTS SC3 (commensal mode):

-Added gen_beamlet_lookup.py which generates a corresponding VHD file.
-Added the above VHD file to all hdllib.cfg files.

applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg

@@ -8,6 +8,7 @@ synth_files =
     src/vhdl/apertif_unb1_correlator_pkg.vhd
     src/vhdl/apertif_unb1_chan320_packetizer.vhd
     src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    src/vhdl/beamlet_lookup.vhd
     src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     src/vhdl/node_apertif_unb1_correlator_input.vhd
     src/vhdl/node_apertif_unb1_correlator_mesh.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_bg_output/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_bm6_bg_ch320/hdllib.cfg

@@ -10,6 +10,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg

@@ -8,6 +8,7 @@ synth_files =
     $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_filter/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg

@@ -10,6 +10,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full_bg/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full_bg_int/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full_bm6/hdllib.cfg

@@ -10,6 +10,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_chan320_packetizer.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full_no_fft/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg_8/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_distr_ref/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd    
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_ref/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_rx_only/hdllib.cfg

@@ -9,6 +9,7 @@ synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_simple/hdllib.cfg

@@ -8,6 +8,7 @@ synth_files =
     $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_simple/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/revisions/sim_apertif_unb1_correlator_nodes/hdllib.cfg

@@ -7,6 +7,7 @@ hdl_lib_technology = ip_stratixiv
 synth_files =
     ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
     ../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
+    ../../src/vhdl/beamlet_lookup.vhd
     ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
     ../../src/vhdl/node_apertif_unb1_correlator_processing_acc_flush_sync.vhd

applications/apertif/designs/apertif_unb1_correlator/src/python/gen_beamlet_lookup.py

+# Author:
+# . Daniel van der Schuur
+# Purpose:
+# . Print beamlet mappings of Imaging vs. Time domain (ARTS SC4, SC3).
+# . Generate the corresponding lookup table as VHDL code.
+
+import numpy as np
+np.set_printoptions(linewidth=250)
+
+print '\nBeamlet mapping (24 subbands*40 CB = 960 beamlets) used for imaging, "300MHz_40CB":'
+b = range(240)+range(256, 256+240)+range(512, 512+240)+range(768, 768+240) # Used beamlets
+i = np.array(b).reshape(24,40) # i contains beamlet mapping for Imaging
+print i
+
+print '\nBeamlet mapping (24 subbands*40 CB = 960 beamlets) used for time domain, "arts_sc4":'
+t = np.copy(i) # t contains beamlet mapping for Time domain
+for cb in range(5): t[:,   cb] = range(    cb*48,    cb*48+48,2) # CB  0...4: beamlets   0,  2,.., 238
+for cb in range(5): t[:, 5+cb] = range(256+cb*48,256+cb*48+48,2) # CB  5...9: beamlets 256,258,.., 494
+for cb in range(5): t[:,10+cb] = range(512+cb*48,512+cb*48+48,2) # CB 10..14: beamlets 512,514,.., 750
+for cb in range(5): t[:,15+cb] = range(768+cb*48,768+cb*48+48,2) # CB 15..19: beamlets 768,770,..,1006
+for cb in range(5): t[:,20+cb] = range(  1+cb*48,  1+cb*48+48,2) # CB 20..24: beamlets   1,  3,.., 239
+for cb in range(5): t[:,25+cb] = range(257+cb*48,257+cb*48+48,2) # CB 25..29: beamlets 257,259,.., 495
+for cb in range(5): t[:,30+cb] = range(513+cb*48,513+cb*48+48,2) # CB 30..34: beamlets 513,515,.., 751
+for cb in range(5): t[:,35+cb] = range(769+cb*48,769+cb*48+48,2) # CB 35..39: beamlets 769,771,..,1007
+print t
+
+print 'Generating VHDL file with lookup table [time domain beamlet] -> [imaging beamlet]: ../vhdl/beamlet_lookup.vhd'
+
+lookup_list = []
+for bt,bi in zip(np.nditer(t), np.nditer(i)):
+    lookup_list.append((int(bt),int(bi)))
+lookup_list.sort(key=lambda tup: tup[0]) # Sort the list so we get incrementing addresses (beamlet_in)
+
+head = """LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- This file was generated by ../python/gen_beamlet_lookup.py
+
+ENTITY beamlet_lookup IS
+  PORT (
+    clk         : IN  STD_LOGIC;
+    beamlet_in  : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+    beamlet_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+  );
+END beamlet_lookup;
+
+ARCHITECTURE rtl OF beamlet_lookup IS
+BEGIN
+PROCESS(clk)
+  BEGIN
+  IF rising_edge(clk) THEN
+    CASE beamlet_in IS
+"""
+
+tail = """      WHEN OTHERS => beamlet_out <= "0000000000";
+    END CASE;
+  END IF;
+END PROCESS;
+END rtl;
+"""
+
+with open('../vhdl/beamlet_lookup.vhd', 'w') as f:
+    f.write(head)
+    for beamlet_mapping in lookup_list:
+        address  = str(bin(beamlet_mapping[0])[2:].zfill(10))
+        data_out = str(bin(beamlet_mapping[1])[2:].zfill(10))
+        line = '      WHEN "'+address+'" => beamlet_out <= "'+data_out+'";\n'
+        f.write(line)
+    f.write(tail)
+f.close()
+