Skip to content
Snippets Groups Projects
Commit c1ef8370 authored by Pieter Donker's avatar Pieter Donker
Browse files

some cleanup

parent 1d34c42d
No related branches found
No related tags found
2 merge requests!28Master,!13Resolve STAT-266
Hide whitespace changes
Inline Side-by-side
boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+ 21
− 1
View file @ c1ef8370
......@@ -97,6 +97,9 @@ ARCHITECTURE str OF unb2b_arp_ping IS
SIGNAL st_rst : STD_LOGIC;
SIGNAL st_clk : STD_LOGIC;
SIGNAL app_led_red : STD_LOGIC := '1';
SIGNAL app_led_green : STD_LOGIC := '0';
-- PIOs
SIGNAL pout_wdi : STD_LOGIC := '0';
SIGNAL wdi_cnt : INTEGER := 0;
......@@ -203,7 +206,9 @@ BEGIN
g_factory_image => g_factory_image,
g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
g_protect_addr_range => g_protect_addr_range
g_protect_addr_range => g_protect_addr_range,
g_app_led_red => TRUE,
g_app_led_green => TRUE
)
PORT MAP (
-- Clock an reset signals
......@@ -221,6 +226,9 @@ BEGIN
dp_rst_in => st_rst,
dp_clk_in => st_clk,
app_led_red => app_led_red,
app_led_green => app_led_green,
-- Toggle WDI
pout_wdi => pout_wdi,
......@@ -323,9 +331,21 @@ BEGIN
eth1g_mm_rst <= mm_rst;
-- led control
p_led : PROCESS(eth1g_reg_interrupt)
BEGIN
IF rising_edge(eth1g_reg_interrupt) THEN
app_led_red <= '0';
app_led_green <= NOT app_led_green;
END IF;
END PROCESS;
--u_eth1g_master : ENTITY eth1g_lib.eth1g_master(beh)
u_eth1g_master : ENTITY eth1g_lib.eth1g_master(rtl)
GENERIC MAP (
g_sim => g_sim
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
......
libraries/io/eth1g/src/vhdl/eth1g_master.vhd
+ 56
− 58
View file @ c1ef8370
......@@ -43,6 +43,9 @@ USE work.eth1g_mem_pkg.ALL;
ENTITY eth1g_master IS
GENERIC (
g_sim : BOOLEAN := FALSE -- when true speed up led toggling in simulation
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
......@@ -114,7 +117,7 @@ ARCHITECTURE rtl OF eth1g_master IS
TYPE t_state IS (s_rst,
s_wr_demux_0, s_wr_demux_1, s_wr_demux_2, s_rd_demux_0, s_rd_demux_1, s_rd_demux_2,
s_wr_config_0, s_wr_config_1, s_wr_config_2, s_wr_config_3, s_wr_control_0,
s_rd_tse_rev, s_wr_tse_if_mode, s_wr_tse_control, s_wr_tse_promis_en, s_wr_tse_mac_0, s_wr_tse_mac_1, s_wr_tse_tx_ipg_len, s_wr_tse_frm_len,
s_rd_tse_rev, s_wr_tse_if_mode, s_rd_tse_control, s_rd_tse_status, s_wr_tse_control, s_wr_tse_promis_en, s_wr_tse_mac_0, s_wr_tse_mac_1, s_wr_tse_tx_ipg_len, s_wr_tse_frm_len,
s_wr_tse_rx_section_empty, s_wr_tse_rx_section_full, s_wr_tse_tx_section_empty, s_wr_tse_tx_section_full,
s_wr_tse_rx_almost_empty, s_wr_tse_rx_almost_full, s_wr_tse_tx_almost_empty, s_wr_tse_tx_almost_full,
s_wait_interrupt_1, s_wait_interrupt_0, s_rd_payload, s_wr_payload, s_wr_control, s_eth_continue);
......@@ -226,20 +229,25 @@ BEGIN
ram_rd_valid <= lat_ram_vec(c_mem_ram_rd_latency);
p_comb : PROCESS (r, reg_miso, ram_miso, tse_miso, reg_interrupt, mm_init, reg_rd_valid, ram_rd_valid)
p_comb : PROCESS (r.state, reg_miso, ram_miso, tse_miso, reg_interrupt, mm_init, reg_rd_valid, ram_rd_valid)
VARIABLE v : t_reg;
VARIABLE v_eth_control_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
BEGIN
-- default assignment
v := r;
v.tse_mosi.wr := '0';
v.tse_mosi.rd := '0';
IF tse_miso.waitrequest = '0' THEN
v.tse_mosi.wr := '0';
v.tse_mosi.rd := '0';
END IF;
v.reg_mosi.wr := '0';
v.reg_mosi.rd := '0';
v.ram_mosi.wr := '0';
v.ram_mosi.rd := '0';
eth_mm_reg_status <= c_eth_mm_reg_status_rst;
eth_mm_reg_control <= c_eth_mm_reg_control_rst;
CASE r.state IS
WHEN s_rst =>
v := (c_mem_mosi_rst, c_mem_mosi_rst, c_mem_mosi_rst, '1', '1', '0', 0, s_rst); -- reset all
......@@ -250,6 +258,7 @@ BEGIN
WHEN s_wr_demux_0 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi+0, c_udp_port_en+c_udp_port_st0, v.reg_mosi); v.state := s_wr_demux_1;
WHEN s_wr_demux_1 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi+1, c_udp_port_en+c_udp_port_st1, v.reg_mosi); v.state := s_wr_demux_2;
WHEN s_wr_demux_2 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi+2, c_udp_port_en+c_udp_port_st2, v.reg_mosi); v.state := s_rd_demux_0;
--WHEN s_wr_demux_2 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi+2, c_udp_port_en+c_udp_port_st2, v.reg_mosi); v.state := s_wr_config_0;
WHEN s_rd_demux_0 => -- read back demux_0 settings
IF lat_reg_rd = '0' THEN proc_eth1g_mem_mm_bus_rd(c_eth_reg_demux_wi+0, v.reg_mosi);
ELSIF reg_rd_valid = '1' THEN v.state := s_rd_demux_1;
......@@ -267,6 +276,7 @@ BEGIN
WHEN s_wr_config_2 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_config_wi+2, src_ip, v.reg_mosi); v.state := s_wr_config_3;
WHEN s_wr_config_3 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_config_wi+3, c_udp_port_ctrl, v.reg_mosi); v.state := s_wr_control_0;
WHEN s_wr_control_0 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_control_rx_en, v.reg_mosi); v.state := s_rd_tse_rev;
--WHEN s_wr_control_0 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_control_rx_en, v.reg_mosi); v.state := s_wr_tse_if_mode;
-- -- start tse setup -- --
WHEN s_rd_tse_rev =>
......@@ -277,133 +287,121 @@ BEGIN
v.state := s_wr_tse_if_mode;
WHEN s_wr_tse_if_mode =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.rd := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#28#), 16#0008#, v.tse_mosi);
v.state := s_rd_tse_control;
END IF;
WHEN s_rd_tse_control =>
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_rd(func_tech_tse_map_pcs_addr(16#00#), v.tse_mosi);
v.state := s_rd_tse_status;
END IF;
WHEN s_rd_tse_status =>
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_rd(func_tech_tse_map_pcs_addr(16#02#), v.tse_mosi);
v.state := s_wr_tse_control;
END IF;
WHEN s_wr_tse_control =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi); -- PSC control, Auto negotiate disable
--proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#1140#, v.tse_mosi); -- PSC control, Auto negotiate enable
IF tse_miso.waitrequest = '0' THEN
IF g_sim = TRUE THEN
proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi); -- PSC control, Auto negotiate disable
ELSE
proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi); -- PSC control, Auto negotiate disable
--proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#1140#, v.tse_mosi); -- PSC control, Auto negotiate enable
END IF;
v.state := s_wr_tse_promis_en;
END IF;
WHEN s_wr_tse_promis_en =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
v.tse_psc_access := '0';
IF c_promis_en = FALSE THEN proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100004B#, v.tse_mosi); -- MAC control
ELSE proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100005B#, v.tse_mosi); END IF;
IF c_promis_en = FALSE THEN
proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100004B#, v.tse_mosi); -- MAC control
ELSE
proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100005B#, v.tse_mosi);
END IF;
v.state := s_wr_tse_mac_0;
END IF;
WHEN s_wr_tse_mac_0 =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#00C#, src_mac_0, v.tse_mosi); -- MAC_0
v.state := s_wr_tse_mac_1;
END IF;
WHEN s_wr_tse_mac_1 =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#010#, src_mac_1, v.tse_mosi); -- MAC_1 <-- SRC_MAC
v.state := s_wr_tse_tx_ipg_len;
END IF;
WHEN s_wr_tse_tx_ipg_len =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#05C#, 16#0000000C#, v.tse_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
v.state := s_wr_tse_frm_len;
END IF;
WHEN s_wr_tse_frm_len =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
--proc_eth1g_mem_mm_bus_wr(16#014#, 16#000005EE#, v.tse_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
proc_eth1g_mem_mm_bus_wr(16#014#, 16#0000233A#, v.tse_mosi); -- FRM_LENGTH <-- receive max frame length = 9018
v.state := s_wr_tse_rx_section_empty;
END IF;
WHEN s_wr_tse_rx_section_empty =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#01C#, c_tech_tse_rx_fifo_depth-16, v.tse_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
v.state := s_wr_tse_rx_section_full;
END IF;
WHEN s_wr_tse_rx_section_full =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#020#, 16, v.tse_mosi); -- RX_SECTION_FULL <-- default 16
v.state := s_wr_tse_tx_section_empty;
END IF;
WHEN s_wr_tse_tx_section_empty =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#024#, c_tech_tse_tx_fifo_depth-16, v.tse_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
v.state := s_wr_tse_tx_section_full;
END IF;
WHEN s_wr_tse_tx_section_full =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#028#, 16, v.tse_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
v.state := s_wr_tse_rx_almost_empty;
END IF;
WHEN s_wr_tse_rx_almost_empty =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#02C#, 8, v.tse_mosi); -- RX_ALMOST_EMPTY <-- default 8
v.state := s_wr_tse_rx_almost_full;
END IF;
WHEN s_wr_tse_rx_almost_full =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#030#, 8, v.tse_mosi); -- RX_ALMOST_FULL <-- default 8
v.state := s_wr_tse_tx_almost_empty;
END IF;
WHEN s_wr_tse_tx_almost_empty =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#034#, 8, v.tse_mosi); -- TX_ALMOST_EMPTY <-- default 8
v.state := s_wr_tse_tx_almost_full;
END IF;
WHEN s_wr_tse_tx_almost_full =>
IF tse_miso.waitrequest = '1' THEN
v.tse_mosi.wr := '1';
ELSE
IF tse_miso.waitrequest = '0' THEN
proc_eth1g_mem_mm_bus_wr(16#038#, c_tech_tse_tx_ready_latency+3, v.tse_mosi); -- TX_ALMOST_FULL <-- default 3
v.state := s_wait_interrupt_1; v.tse_init := '0';
v.state := s_wait_interrupt_1;
v.tse_init := '0';
END IF;
-- -- start control loop -- --
WHEN s_wait_interrupt_1 =>
eth_mm_reg_status <= c_eth_mm_reg_status_rst;
eth_mm_reg_control <= c_eth_mm_reg_control_rst;
IF reg_interrupt = '1' THEN
IF lat_reg_rd = '0' THEN proc_eth1g_mem_mm_bus_rd(c_eth_reg_status_wi+0, v.reg_mosi); -- read status register to read the status
ELSIF reg_rd_valid = '1' THEN
......@@ -444,8 +442,8 @@ BEGIN
END IF;
WHEN s_wr_control =>
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_eth1g_mem_mm_bus_wr(c_eth_reg_control_wi+0, TO_UINT(v_eth_control_word), v.reg_mosi); v.state := s_eth_continue;
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_eth1g_mem_mm_bus_wr(c_eth_reg_control_wi+0, TO_UINT(v_eth_control_word), v.reg_mosi); v.state := s_eth_continue;
WHEN s_eth_continue => proc_eth1g_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, v.reg_mosi); v.state := s_wait_interrupt_1; -- write continue register to make the ETH module continue
WHEN OTHERS => NULL;
END CASE;
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment