Moved the ip_stratixiv single file IP from library ip_stratixiv to separate...

Moved the ip_stratixiv single file IP from library ip_stratixiv to separate sub libraries, similar as for ip_arria10.

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses = technology ip_stratixiv ip_arria10_fifo
+hdl_lib_uses = technology ip_stratixiv_fifo ip_arria10_fifo
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR

libraries/technology/flash/hdllib.cfg

 hdl_lib_name = tech_flash
 hdl_library_clause_name = tech_flash_lib
-hdl_lib_uses = technology ip_stratixiv
+hdl_lib_uses = technology ip_stratixiv_flash
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR

libraries/technology/iobuf/hdllib.cfg

 hdl_lib_name = tech_iobuf
 hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses = technology ip_stratixiv ip_arria10_ddio
+hdl_lib_uses = technology ip_stratixiv_ddio ip_arria10_ddio
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR

libraries/technology/ip_stratixiv/ddio/hdllib.cfg

+hdl_lib_name = ip_stratixiv_ddio
+hdl_library_clause_name = ip_stratixiv_ddio_lib
+hdl_lib_uses = technology
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    ip_stratixiv_ddio_in.vhd
+    ip_stratixiv_ddio_out.vhd
+    
+test_bench_files =

libraries/technology/ip_stratixiv/fifo/hdllib.cfg

+hdl_lib_name = ip_stratixiv_fifo
+hdl_library_clause_name = ip_stratixiv_fifo_lib
+hdl_lib_uses = technology
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    ip_stratixiv_fifo_dc_mixed_widths.vhd
+    ip_stratixiv_fifo_dc.vhd
+    ip_stratixiv_fifo_sc.vhd
+    
+test_bench_files =

libraries/technology/ip_stratixiv/flash/hdllib.cfg

+hdl_lib_name = ip_stratixiv_flash
+hdl_library_clause_name = ip_stratixiv_flash_lib
+hdl_lib_uses = technology numonyx_m25p128
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    ip_stratixiv_asmi_parallel.vhd
+    ip_stratixiv_remote_update.vhd
+    
+test_bench_files =

libraries/technology/ip_stratixiv/ram/hdllib.cfg

+hdl_lib_name = ip_stratixiv_ram
+hdl_library_clause_name = ip_stratixiv_ram_lib
+hdl_lib_uses = technology
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    ip_stratixiv_ram_crwk_crw.vhd
+    ip_stratixiv_ram_crw_crw.vhd
+    ip_stratixiv_ram_cr_cw.vhd
+    ip_stratixiv_ram_r_w.vhd
+    ip_stratixiv_rom_r.vhd
+    
+test_bench_files =

libraries/technology/ip_stratixiv/readme_ip_stratixiv.txt

@@ -2,59 +2,13 @@ README: Description of the ip_stratixiv library
 
 Contents:
 1) Single file IP
-  a) ip_stratixiv_fifo*
-  b) ip_stratixiv_ram*
-  c) ip_stratixiv_ddio*
-  d) ip_stratixiv_hssi*
-  e) ip_stratixiv_gxb_reconfig*
-  f) ip_stratixiv_asmi_parallel
-  g) ip_stratixiv_remote_update
 2) Multi file IP
-  a) tse_sgmii_lvds, tse_sgmii_gx
-  b) phy_xaui
-  c) mac_10g
-
-
 
 
 
 1) Single file IP
 
-The single file IP is kept flat in the top level ip_<device_name> directory.
-
-a) ip_stratixiv_fifo*
-
-
-b) ip_stratixiv_ram*
-
-
-c) ip_stratixiv_ddio*
-
-
-d) ip_stratixiv_hssi*
-
-
-e) ip_stratixiv_gxb_reconfig*
-
-  In theory the gxb_reconfig IP are the same, but in practise they can differ slightly between different Quartus versions. The tr_nonbonded, tse_sgmii_gx
-  and tr_xaui libraries each use a newly generated gxb_reconfig. Trying to let them all use the latest version of the gxb_reconfig IP would require
-  validation on hardware. To avoid having to do this preserve the various versions of gxb_reconfig that were created in time. Versions overview:
-  
-             reconfig_fromgxb         used in library
-             bus width
-     v9.1  :      g_nof_gx    * 17    tr_nonbonded
-     v10.1 : ceil(g_nof_gx/4) * 17    tse_sgmii_gx
-     v11.1 : ceil(g_nof_gx/4) * 17    tr_xaui
-
- . The gxb_reconfig for v9.1 uses wider reconfig_fromgxb bus width.
- . The reconfig_fromgxb for v10.1 and v11.1 seem idendical except for different internal signal namings.
-   
-
-f) ip_stratixiv_asmi_parallel
-
-
-g) ip_stratixiv_remote_update
-
+The single file IP is grouped in ip_<device_name>/<ip_name> sub directories. Each with itsown hdllib.cfg.
    
 
 
@@ -86,11 +40,3 @@ For simulation the MegaWizard also generates a msim_setup.tcl script. A stripped
 kept in compile_ip.tcl. This compile_ip.tcl only compiles what is needed and is made available in the Modelsim project file via the
 modelsim_compile_ip_files key in the hdllib.cfg. The 'mk' command automatically also executes the compile_ip.tcl before it compiles any other HDL
 in the library.
-
-a) tse_sgmii_lvds, tse_sgmii_gx
-
-
-b) phy_xaui
-
-
-c) mac_10g