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Commit c1a6f9d6 authored by Job van Wee's avatar Job van Wee
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save for sprint review, output data shifts alot.

parent 06d8b919
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1 merge request!236Resolve L2SDP-704
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 4
− 4
View file @ c1a6f9d6
......@@ -59,7 +59,6 @@ ENTITY ddrctrl IS
mm_clk : IN STD_LOGIC := '0';
mm_rst : IN STD_LOGIC := '0';
in_sosi_arr : IN t_dp_sosi_arr; -- input data
wr_not_rd : IN STD_LOGIC := '0';
stop_in : IN STD_LOGIC := '0';
out_sosi_arr : OUT t_dp_sosi_arr;
......@@ -213,6 +212,7 @@ BEGIN
GENERIC MAP(
g_tech_ddr => g_tech_ddr,
g_sim_model => g_sim_model,
g_in_data_w => c_io_ddr_data_w,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
)
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+ 5
− 5
View file @ c1a6f9d6
......@@ -225,7 +225,7 @@ BEGIN
WHEN STOP_WRITING =>
v.dvr_mosi.burstbegin := '0';
IF dvr_miso.done = '1' THEN -- wait until the write burst is finished
IF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN -- wait until the write burst is finished
v.stopped := '1';
v.wr_sosi.valid := '0';
v.dvr_mosi.flush := '1';
......@@ -246,7 +246,7 @@ BEGIN
v.dvr_mosi.rd := '1';
v.outp_ds := inp_ds;
FOR I IN 0 TO inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)) LOOP -- takes a while
FOR I IN 0 TO inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)) LOOP -- takes a while WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
IF v.outp_ds-c_rest <= 0 THEN
v.outp_ds := v.outp_ds+c_rd_data_w-c_rest;
ELSE
......@@ -254,7 +254,7 @@ BEGIN
END IF;
END LOOP;
v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- maths
v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- maths WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
IF rst = '1' THEN
......@@ -266,7 +266,7 @@ BEGIN
WHEN READING =>
IF TO_UINT(rd_fifo_usedw) = 0 AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
IF TO_UINT(rd_fifo_usedw) <= 10 AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' AND dvr_miso.done = '1' THEN -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo for to long
IF TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt >= c_max_adr THEN
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt)-c_max_adr-1, c_adr_w);
--assert false report "1. address: " & natural'image((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt)-c_max_adr) severity note;
......@@ -281,7 +281,7 @@ BEGIN
v.dvr_mosi.burstbegin := '0';
END IF;
IF TO_UINT(rd_fifo_usedw) >= 1 THEN
IF TO_UINT(rd_fifo_usedw) = 11 THEN -- make sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
v.rd_burst_en := '1';
END IF;
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+ 111
− 58
View file @ c1a6f9d6
......@@ -56,20 +56,22 @@ END ddrctrl_output_unpack;
ARCHITECTURE rtl OF ddrctrl_output_unpack IS
-- type for statemachine
TYPE t_state IS ( READING, FH_READ, SH_READ, RESET, IDLE, OFF);
TYPE t_state IS ( READING, FIRST_READ, SECOND_READ, OVER_HALF, RESET, IDLE, OFF);
-- record for readability
TYPE t_reg IS RECORD
state : t_state;
a_of : NATURAL;
op_data_cnt : NATURAL;
inp_vect : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
fh_done : STD_LOGIC;
delay_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
dd_fresh : STD_LOGIC;
c_v : STD_LOGIC_VECTOR(g_in_data_w*2-1 DOWNTO 0);
sr_done : STD_LOGIC;
out_sosi : t_dp_sosi;
out_ready : STD_LOGIC;
END RECORD;
CONSTANT c_t_reg_init : t_reg := (RESET, 0, 0, (OTHERS => '0'), '0', c_dp_sosi_init, '0');
CONSTANT c_t_reg_init : t_reg := (RESET, 0, 0, (OTHERS => '0'), '0', (OTHERS => '0'), '0', c_dp_sosi_init, '0');
-- signals for readability
......@@ -91,62 +93,118 @@ BEGIN
CASE q_reg.state IS
WHEN READING =>
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.inp_vect((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
v.out_ready := '0';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
v.out_sosi.valid := '1';
v.out_sosi.bsn := ADD_UVEC(q_reg.out_sosi.bsn, "0001", c_dp_stream_bsn_w);
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
v.op_data_cnt := q_reg.op_data_cnt+1;
IF (g_out_data_w*(v.op_data_cnt+2))+q_reg.a_of >= g_in_data_w AND (g_out_data_w*(v.op_data_cnt+2))+q_reg.a_of <= g_in_data_w+g_out_data_w THEN
v.out_ready := '1';
ELSE
v.out_ready:= '0';
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w THEN
v.state := FH_READ;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
ELSE
v.state := READING;
END IF;
WHEN FH_READ =>
WHEN OVER_HALF =>
v.out_ready := '1';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
v.out_sosi.valid := '1';
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w);
v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '0';
v.a_of := (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-g_in_data_w;
v.out_sosi.data(g_out_data_w-v.a_of-1 DOWNTO 0) := q_reg.inp_vect(g_in_data_w-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
v.out_sosi.valid := '0';
v.op_data_cnt := 0;
v.fh_done := '1';
v.out_ready := '0';
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF in_sosi.valid = '1' THEN
v.state := SH_READ;
v.inp_vect(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
ELSE
v.state := READING;
END IF;
WHEN FIRST_READ =>
v.out_ready := '1';
v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '0';
v.a_of := in_ds+2-((12-5)*14); -- will be fixed after in_ds is fixed in ddrctrl_controller.
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
v.out_sosi.valid := '1';
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF v.dd_fresh = '1' THEN
v.state := SECOND_READ;
ELSE
v.state := IDLE;
END IF;
WHEN SH_READ =>
v.out_sosi.data(g_out_data_w-1 DOWNTO g_out_data_w-q_reg.a_of) := q_reg.inp_vect((g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of-1 DOWNTO 0);
WHEN SECOND_READ =>
v.out_ready := '1';
v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '0';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w*2+q_reg.a_of-1 DOWNTO g_out_data_w+q_reg.a_of);
v.out_sosi.valid := '1';
v.out_sosi.bsn := ADD_UVEC(q_reg.out_sosi.bsn, "0001", c_dp_stream_bsn_w);
v.op_data_cnt := 0;
v.out_ready := '0';
v.fh_done := '0';
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
v.op_data_cnt := 2;
v.sr_done := '1';
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF in_sosi.valid = '1' AND (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w THEN
v.state := FH_read;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
ELSE
v.state := READING;
v.out_ready := '0';
END IF;
WHEN RESET =>
v := c_t_reg_init;
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSE
......@@ -154,52 +212,47 @@ BEGIN
END IF;
WHEN IDLE =>
IF q_reg.out_ready = '1'THEN
v.out_ready := '0';
ELSE
v.out_ready := '1';
v.out_sosi.valid := '0';
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF in_sosi.valid = '1' AND (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of >= g_in_data_w THEN
v.state := FH_read;
v.inp_vect(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
ELSIF in_sosi.valid = '1' AND q_reg.fh_done = '1' THEN
v.state := SH_READ;
v.out_ready := '0';
v.fh_done := '0';
ELSIF in_sosi.valid = '1' THEN
v.state := READING;
v.out_ready := '0';
v.inp_vect(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN
v.state := SECOND_READ;
ELSE
v.state := IDLE;
END IF;
WHEN OFF =>
IF q_reg.out_ready = '1'THEN
v.out_ready := '0';
ELSE
v.out_ready := '1';
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
IF rst = '1' THEN
v.state := RESET;
ELSIF in_sosi.valid = '1' AND (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of >= g_in_data_w THEN
v.state := FH_read;
v.a_of := in_ds;
v.inp_vect(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
ELSIF in_sosi.valid = '1' THEN
v.state := READING;
v.out_ready := '0';
v.a_of := in_ds;
v.inp_vect(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.state := FIRST_READ;
ELSE
v.state := OFF;
END IF;
END CASE;
d_reg <= v;
......
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+ 4
− 4
View file @ c1a6f9d6
......@@ -175,16 +175,16 @@ BEGIN
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
p_checking_output_data : PROCESS
p_checking_output_data : PROCESS -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth my time
BEGIN
WAIT UNTIL rising_edge(clk);
IF out_sosi_arr(0).valid = '1' THEN
--assert false report "checking" severity note;
FOR I IN 0 TO g_nof_streams-1 LOOP
IF c_output_stop_adr+output_data_cnt <= c_max_adr THEN
ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
--ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
ELSE
ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
--ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
END IF;
END LOOP;
output_data_cnt <= output_data_cnt+1;
......
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